src/soc/decoder/power_enums.py

   1 from enum import Enum, unique
   2 import csv
   3 import os
   4 import requests
   5
   6
   7 def download_wiki_file(name):
   8     file_dir = os.path.dirname(os.path.realpath(__file__))
   9     file_path = os.path.join(file_dir, name)
  10     if not os.path.isfile(file_path):
  11         url = 'https://libre-riscv.org/openpower/isatables/' + name
  12         r = requests.get(url, allow_redirects=True)
  13         with open(file_path, 'w') as outfile:
  14             outfile.write(r.content.decode("utf-8"))
  15     return file_path
  16
  17
  18 def get_csv(name):
  19     file_path = download_wiki_file(name)
  20     with open(file_path, 'r') as csvfile:
  21         reader = csv.DictReader(csvfile)
  22         return list(reader)
  23
  24
  25 # names of the fields in the tables that don't correspond to an enum
  26 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
  27                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
  28                     'sgn', 'lk', 'sgl pipe']
  29
  30 # default values for fields in the table
  31 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  32                    'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  33                    'ldst len': 'NONE',
  34                    'rc' : 'NONE', 'cry in' : 'ZERO', 'form': 'NONE'}
  35
  36 def get_signal_name(name):
  37     if name[0].isdigit():
  38         name = "is_" + name
  39     return name.lower().replace(' ', '_')
  40
  41
  42 @unique
  43 class Function(Enum):
  44     NONE = 0
  45     ALU = 1
  46     LDST = 2
  47
  48
  49 @unique
  50 class Form(Enum):
  51     NONE = 0
  52     I = 1
  53     B = 2
  54     SC = 3
  55     D = 4
  56     DS = 5
  57     DQ = 6
  58     DX = 7
  59     X = 8
  60     XL = 9
  61     XFX = 10
  62     XFL = 11
  63     XX1 = 12
  64     XX2 = 13
  65     XX3 = 14
  66     XX4 = 15
  67     XS = 16
  68     XO = 17
  69     A = 18
  70     M = 19
  71     MD = 20
  72     MDS = 21
  73     VA = 22
  74     VC = 23
  75     VX = 24
  76     EVX = 25
  77     EVS = 26
  78     Z22 = 27
  79     Z23 = 28
  80
  81
  82 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
  83 @unique
  84 class InternalOp(Enum):
  85     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
  86     OP_NOP = 1
  87     OP_ADD = 2
  88     OP_ADDPCIS = 3
  89     OP_AND = 4
  90     OP_ATTN = 5
  91     OP_B = 6
  92     OP_BC = 7
  93     OP_BCREG = 8
  94     OP_BPERM = 9
  95     OP_CMP = 10
  96     OP_CMPB = 11
  97     OP_CMPEQB = 12
  98     OP_CMPRB = 13
  99     OP_CNTZ = 14
 100     OP_CRAND = 15
 101     OP_CRANDC = 16
 102     OP_CREQV = 17
 103     OP_CRNAND = 18
 104     OP_CRNOR = 19
 105     OP_CROR = 20
 106     OP_CRORC = 21
 107     OP_CRXOR = 22
 108     OP_DARN = 23
 109     OP_DCBF = 24
 110     OP_DCBST = 25
 111     OP_DCBT = 26
 112     OP_DCBTST = 27
 113     OP_DCBZ = 28
 114     OP_DIV = 29
 115     OP_DIVE = 30
 116     OP_EXTS = 31
 117     OP_EXTSWSLI = 32
 118     OP_ICBI = 33
 119     OP_ICBT = 34
 120     OP_ISEL = 35
 121     OP_ISYNC = 36
 122     OP_LOAD = 37
 123     OP_STORE = 38
 124     OP_MADDHD = 39
 125     OP_MADDHDU = 40
 126     OP_MADDLD = 41
 127     OP_MCRF = 42
 128     OP_MCRXR = 43
 129     OP_MCRXRX = 44
 130     OP_MFCR = 45
 131     OP_MFSPR = 46
 132     OP_MOD = 47
 133     OP_MTCRF = 48
 134     OP_MTSPR = 49
 135     OP_MUL_L64 = 50
 136     OP_MUL_H64 = 51
 137     OP_MUL_H32 = 52
 138     OP_OR = 53
 139     OP_POPCNT = 54
 140     OP_PRTY = 55
 141     OP_RLC = 56
 142     OP_RLCL = 57
 143     OP_RLCR = 58
 144     OP_SETB = 59
 145     OP_SHL = 60
 146     OP_SHR = 61
 147     OP_SYNC = 62
 148     OP_TD = 63
 149     OP_TDI = 64
 150     OP_TW = 65
 151     OP_TWI = 66
 152     OP_XOR = 67
 153     OP_SIM_CONFIG = 68
 154
 155
 156 @unique
 157 class In1Sel(Enum):
 158     NONE = 0
 159     RA = 1
 160     RA_OR_ZERO = 2
 161     SPR = 3
 162
 163
 164 @unique
 165 class In2Sel(Enum):
 166     NONE = 0
 167     RB = 1
 168     CONST_UI = 2
 169     CONST_SI = 3
 170     CONST_UI_HI = 4
 171     CONST_SI_HI = 5
 172     CONST_LI = 6
 173     CONST_BD = 7
 174     CONST_DS = 8
 175     CONST_M1 = 9
 176     CONST_SH = 10
 177     CONST_SH32 = 11
 178     SPR = 12
 179
 180
 181 @unique
 182 class In3Sel(Enum):
 183     NONE = 0
 184     RS = 1
 185
 186
 187 @unique
 188 class OutSel(Enum):
 189     NONE = 0
 190     RT = 1
 191     RA = 2
 192     SPR = 3
 193
 194
 195 @unique
 196 class LdstLen(Enum):
 197     NONE = 0
 198     is1B = 1
 199     is2B = 2
 200     is4B = 3
 201     is8B = 4
 202
 203
 204 @unique
 205 class RC(Enum):
 206     NONE = 0
 207     ONE = 1
 208     RC = 2
 209
 210
 211 @unique
 212 class CryIn(Enum):
 213     ZERO = 0
 214     ONE = 1
 215     CA = 2
 216
 217
 218 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 219 # http://libre-riscv.org/openpower/isatables/sprs.csv
 220 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 221
 222 spr_csv = get_csv("sprs.csv")
 223 fields = [(row['SPR'], row['Idx']) for row in spr_csv]
 224 SPR = Enum('SPR', fields)