1 from enum
import Enum
, unique
4 from os
.path
import dirname
, join
6 def find_wiki_file(name
):
7 filedir
= os
.path
.dirname(os
.path
.abspath(__file__
))
8 basedir
= dirname(dirname(dirname(filedir
)))
9 tabledir
= join(basedir
, 'libreriscv')
10 tabledir
= join(tabledir
, 'openpower')
11 tabledir
= join(tabledir
, 'isatables')
13 file_path
= join(tabledir
, name
)
18 file_path
= find_wiki_file(name
)
19 with
open(file_path
, 'r') as csvfile
:
20 reader
= csv
.DictReader(csvfile
)
24 # names of the fields in the tables that don't correspond to an enum
25 single_bit_flags
= ['CR in', 'CR out', 'inv A', 'inv out',
26 'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
27 'sgn', 'lk', 'sgl pipe']
29 # default values for fields in the table
30 default_values
= {'unit': "NONE", 'internal op': "OP_ILLEGAL",
31 'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
33 'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
36 def get_signal_name(name
):
39 return name
.lower().replace(' ', '_')
82 # Internal Operation numbering. Add new opcodes here (FPADD, FPMUL etc.)
84 class InternalOp(Enum
):
85 OP_ILLEGAL
= 0 # important that this is zero (see power_decoder.py)
218 # SPRs - Special-Purpose Registers. See V3.0B Figure 18 p971 and
219 # http://libre-riscv.org/openpower/isatables/sprs.csv
220 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
222 spr_csv
= get_csv("sprs.csv")
223 fields
= [(row
['SPR'], int(row
['Idx'])) for row
in spr_csv
]
224 SPR
= Enum('SPR', fields
)