src/soc/decoder/power_fieldsn.py

   1 from collections import OrderedDict
   2 from soc.decoder.power_fields import DecodeFields, BitRange
   3 from nmigen import Module, Elaboratable, Signal, Cat
   4 from nmigen.cli import rtlil
   5 from copy import deepcopy
   6
   7
   8 class SignalBitRange(BitRange):
   9     def __init__(self, signal):
  10         BitRange.__init__(self)
  11         self.signal = signal
  12
  13     def __deepcopy__(self, memo):
  14         signal = deepcopy(self.signal, memo)
  15         retval = SignalBitRange(signal=signal)
  16         for k, v in self.items():
  17             k = deepcopy(k, memo)
  18             v = deepcopy(v, memo)
  19             retval[k] = v
  20         return retval
  21
  22     def _rev(self, k):
  23         width = self.signal.width
  24         return width-1-k
  25
  26     def __getitem__(self, subs):
  27         # *sigh* field numberings are bit-inverted.  PowerISA 3.0B section 1.3.2
  28         if isinstance(subs, slice):
  29             res = []
  30             start, stop, step = subs.start, subs.stop, subs.step
  31             if step is None:
  32                 step = 1
  33             if start is None:
  34                 start = 0
  35             if stop is None:
  36                 stop = -1
  37             if start < 0:
  38                 start = len(self) + start + 1
  39             if stop < 0:
  40                 stop = len(self) + stop + 1
  41             for t in range(start, stop, step):
  42                 t = len(self) - 1 - t  # invert field back
  43                 k = OrderedDict.__getitem__(self, t)
  44                 res.append(self.signal[self._rev(k)])  # reverse-order here
  45             return Cat(*res)
  46         else:
  47             if subs < 0:
  48                 subs = len(self) + subs
  49             subs = len(self) - 1 - subs  # invert field back
  50             k = OrderedDict.__getitem__(self, subs)
  51             return self.signal[self._rev(k)]  # reverse-order here
  52
  53
  54 class SigDecode(Elaboratable):
  55
  56     def __init__(self, width):
  57         self.opcode_in = Signal(width, reset_less=False)
  58         self.df = DecodeFields(SignalBitRange, [self.opcode_in])
  59         self.df.create_specs()
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63         comb = m.d.comb
  64         return m
  65
  66     def ports(self):
  67         return [self.opcode_in]
  68
  69
  70 def create_sigdecode():
  71     s = SigDecode(32)
  72     return s
  73
  74
  75 if __name__ == '__main__':
  76     sigdecode = create_sigdecode()
  77     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
  78     with open("decoder.il", "w") as f:
  79         f.write(vl)