1 from collections
import OrderedDict
2 from soc
.decoder
.power_fields
import DecodeFields
, BitRange
3 from nmigen
import Module
, Elaboratable
, Signal
, Cat
4 from nmigen
.cli
import rtlil
7 class SignalBitRange(BitRange
):
8 def __init__(self
, signal
):
9 BitRange
.__init
__(self
)
13 width
= self
.signal
.shape()[0]
16 def __getitem__(self
, subs
):
17 # *sigh* field numberings are bit-inverted. PowerISA 3.0B section 1.3.2
20 if isinstance(subs
, slice):
23 start
, stop
, step
= subs
.start
, subs
.stop
, subs
.step
31 start
= len(self
) - start
- 1
33 stop
= len(self
) - stop
- 1
34 print ("range", start
, stop
, step
)
35 for t
in range(start
, stop
, step
):
36 k
= OrderedDict
.__getitem
__(self
, t
)
38 res
.append(self
.signal
[self
._rev
(k
)]) # reverse-order here
41 k
= OrderedDict
.__getitem
__(self
, subs
)
42 return self
.signal
[self
._rev
(k
)] # reverse-order here
44 print ("translated", subs
, translated
)
47 class SigDecode(Elaboratable
):
49 def __init__(self
, width
):
50 self
.opcode_in
= Signal(width
, reset_less
=False)
51 self
.df
= DecodeFields(SignalBitRange
, [self
.opcode_in
])
52 self
.df
.create_specs()
53 self
.x_s
= Signal(len(self
.df
.FormX
.S
), reset_less
=True)
54 self
.x_sh
= Signal(len(self
.df
.FormX
.SH
), reset_less
=True)
55 self
.dq_xs_s
= Signal(len(self
.df
.FormDQ
.SX_S
), reset_less
=True)
57 def elaborate(self
, platform
):
60 comb
+= self
.x_s
.eq(self
.df
.FormX
.S
[0])
61 comb
+= self
.x_sh
.eq(self
.df
.FormX
.SH
[0:-1])
62 comb
+= self
.dq_xs_s
.eq(self
.df
.FormDQ
.SX_S
[0:-1])
66 return [self
.opcode_in
, self
.x_s
, self
.x_sh
]
68 def create_sigdecode():
72 if __name__
== '__main__':
73 sigdecode
= create_sigdecode()
74 vl
= rtlil
.convert(sigdecode
, ports
=sigdecode
.ports())
75 with
open("decoder.il", "w") as f
: