src/soc/decoder/power_fieldsn.py

   1 from collections import OrderedDict
   2 from soc.decoder.power_fields import DecodeFields, BitRange
   3 from nmigen import Module, Elaboratable, Signal, Cat
   4 from nmigen.cli import rtlil
   5
   6
   7 class SignalBitRange(BitRange):
   8     def __init__(self, signal):
   9         BitRange.__init__(self)
  10         self.signal = signal
  11
  12     def _rev(self, k):
  13         width = self.signal.shape()[0]
  14         return width-1-k
  15
  16     def __getitem__(self, subs):
  17         # *sigh* field numberings are bit-inverted.  PowerISA 3.0B section 1.3.2
  18         if isinstance(subs, slice):
  19             res = []
  20             start, stop, step = subs.start, subs.stop, subs.step
  21             if step is None:
  22                 step = 1
  23             if start is None:
  24                 start = 0
  25             if stop is None:
  26                 stop = -1
  27             if start < 0:
  28                 start = len(self) + start + 1
  29             if stop < 0:
  30                 stop = len(self) + stop + 1
  31             for t in range(start, stop, step):
  32                 t = len(self) - 1 - t  # invert field back
  33                 k = OrderedDict.__getitem__(self, t)
  34                 res.append(self.signal[self._rev(k)])  # reverse-order here
  35             return Cat(*res)
  36         else:
  37             if subs < 0:
  38                 subs = len(self) + subs
  39             subs = len(self) - 1 - subs  # invert field back
  40             k = OrderedDict.__getitem__(self, subs)
  41             return self.signal[self._rev(k)]  # reverse-order here
  42
  43
  44 class SigDecode(Elaboratable):
  45
  46     def __init__(self, width):
  47         self.opcode_in = Signal(width, reset_less=False)
  48         self.df = DecodeFields(SignalBitRange, [self.opcode_in])
  49         self.df.create_specs()
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53         comb = m.d.comb
  54         return m
  55
  56     def ports(self):
  57         return [self.opcode_in]
  58
  59
  60 def create_sigdecode():
  61     s = SigDecode(32)
  62     return s
  63
  64
  65 if __name__ == '__main__':
  66     sigdecode = create_sigdecode()
  67     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
  68     with open("decoder.il", "w") as f:
  69         f.write(vl)