src/soc/decoder/power_regspec_map.py

   1 """regspec_decode
   2
   3 functions for the relationship between regspecs and Decode2Execute1Type
   4
   5 these functions encodes the understanding (relationship) between
   6 Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2).
   7
   8 based on the regspec, which contains the register file name and register
   9 name, return a tuple of:
  10
  11 * how the decoder should determine whether the Function Unit needs
  12   access to a given Regport or not
  13 * which Regfile number on that port should be read to get that data
  14 * when it comes to writing: likewise, which Regfile num should be written
  15
  16 Note that some of the port numbering encoding is *unary*.  in the case
  17 of "Full Condition Register", it's a full 8-bit mask of read/write-enables.
  18 This actually matches directly with the XFX field in MTCR, and at
  19 some point that 8-bit mask from the instruction could actually be passed
  20 directly through to full_cr (TODO).
  21
  22 For the INT and CR numbering, these are expressed in binary in the
  23 instruction and need to be converted to unary (1<<read_reg1.data).
  24 Note however that XFX in MTCR is unary-masked!
  25
  26 XER regs are implicitly-encoded (hard-coded) based on whether the
  27 operation has carry or overflow.
  28
  29 FAST regfile is, again, implicitly encoded, back in PowerDecode2, based
  30 on the type of operation (see DecodeB for an example, where fast_out
  31 is set, then carried into read_fast2 in PowerDecode2).
  32
  33 The SPR regfile on the other hand is *binary*-encoded, and, furthermore,
  34 has to be "remapped" to internal SPR Enum indices (see SPRMap in PowerDecode2)
  35 see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  36 """
  37 from nmigen import Const
  38 from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs
  39 from soc.decoder.power_enums import CryIn
  40
  41
  42 def regspec_decode_read(e, regfile, name):
  43     """regspec_decode_read
  44     """
  45
  46     # INT regfile
  47
  48     if regfile == 'INT':
  49         # Int register numbering is *unary* encoded
  50         if name == 'ra': # RA
  51             return e.read_reg1.ok, e.read_reg1.data
  52         if name == 'rb': # RB
  53             return e.read_reg2.ok, e.read_reg2.data
  54         if name == 'rc': # RS
  55             return e.read_reg3.ok, e.read_reg3.data
  56
  57     # CR regfile
  58
  59     if regfile == 'CR':
  60         # CRRegs register numbering is *unary* encoded
  61         # *sigh*.  numbering inverted on part-CRs.  because POWER.
  62         if name == 'full_cr': # full CR
  63             return e.do.read_cr_whole, 0b11111111
  64         if name == 'cr_a': # CR A
  65             return e.read_cr1.ok, 1<<(7-e.read_cr1.data)
  66         if name == 'cr_b': # CR B
  67             return e.read_cr2.ok, 1<<(7-e.read_cr2.data)
  68         if name == 'cr_c': # CR C
  69             return e.read_cr3.ok, 1<<(7-e.read_cr3.data)
  70
  71     # XER regfile
  72
  73     if regfile == 'XER':
  74         # XERRegs register numbering is *unary* encoded
  75         SO = 1<<XERRegs.SO
  76         CA = 1<<XERRegs.CA
  77         OV = 1<<XERRegs.OV
  78         if name == 'xer_so':
  79             # SO needs to be read for overflow *and* for creation
  80             # of CR0 and also for MFSPR
  81             return ((e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in |
  82                      (e.do.rc.rc & e.do.rc.ok)), SO
  83         if name == 'xer_ov':
  84             return (e.do.oe.oe[0] & e.do.oe.oe_ok) | e.xer_in, OV
  85         if name == 'xer_ca':
  86             return (e.do.input_carry == CryIn.CA.value) | e.xer_in, CA
  87
  88     # STATE regfile
  89
  90     if regfile == 'STATE':
  91         # STATE register numbering is *unary* encoded
  92         PC = 1<<StateRegs.PC
  93         MSR = 1<<Stateegs.MSR
  94         if name in ['cia', 'nia']:
  95             return Const(1), PC # TODO: detect read-conditions
  96         if name == 'msr':
  97             return Const(1), MSR # TODO: detect read-conditions
  98
  99     # FAST regfile
 100
 101     if regfile == 'FAST':
 102         # FAST register numbering is *unary* encoded
 103         if name == 'fast1':
 104             return e.read_fast1.ok, e.read_fast1.data
 105         if name == 'fast2':
 106             return e.read_fast2.ok, e.read_fast2.data
 107
 108     # SPR regfile
 109
 110     if regfile == 'SPR':
 111         # SPR register numbering is *binary* encoded
 112         if name == 'spr1':
 113             return e.read_spr1.ok, e.read_spr1.data
 114
 115     assert False, "regspec not found %s %s" % (regfile, name)
 116
 117
 118 def regspec_decode_write(e, regfile, name):
 119     """regspec_decode_write
 120     """
 121
 122     # INT regfile
 123
 124     if regfile == 'INT':
 125         # Int register numbering is *unary* encoded
 126         if name == 'o': # RT
 127             return e.write_reg, e.write_reg.data
 128         if name == 'o1': # RA (update mode: LD/ST EA)
 129             return e.write_ea, e.write_ea.data
 130
 131     # CR regfile
 132
 133     if regfile == 'CR':
 134         # CRRegs register numbering is *unary* encoded
 135         # *sigh*.  numbering inverted on part-CRs.  because POWER.
 136         if name == 'full_cr': # full CR
 137             return e.do.write_cr_whole, 0b11111111
 138         if name == 'cr_a': # CR A
 139             return e.write_cr, 1<<(7-e.write_cr.data)
 140
 141     # XER regfile
 142
 143     if regfile == 'XER':
 144         # XERRegs register numbering is *unary* encoded
 145         SO = 1<<XERRegs.SO
 146         CA = 1<<XERRegs.CA
 147         OV = 1<<XERRegs.OV
 148         if name == 'xer_so':
 149             return e.xer_out, SO # hmmm
 150         if name == 'xer_ov':
 151             return e.xer_out, OV # hmmm
 152         if name == 'xer_ca':
 153             return e.xer_out, CA # hmmm
 154
 155     # STATE regfile
 156
 157     if regfile == 'STATE':
 158         # STATE register numbering is *unary* encoded
 159         PC = 1<<StateRegs.PC
 160         MSR = 1<<StateRegs.MSR
 161         if name in ['cia', 'nia']:
 162             return None, PC # hmmm
 163         if name == 'msr':
 164             return None, MSR # hmmm
 165
 166     # FAST regfile
 167
 168     if regfile == 'FAST':
 169         # FAST register numbering is *unary* encoded
 170         if name == 'fast1':
 171             return e.write_fast1, e.write_fast1.data
 172         if name == 'fast2':
 173             return e.write_fast2, e.write_fast2.data
 174
 175     # SPR regfile
 176
 177     if regfile == 'SPR':
 178         # SPR register numbering is *binary* encoded
 179         if name == 'spr1': # SPR1
 180             return e.write_spr, e.write_spr.data
 181
 182     assert False, "regspec not found %s %s" % (regfile, name)
 183