2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
5 from soc.decoder.power_enums import get_csv, find_wiki_dir
6 import os
8 # identifies register by type
9 def is_CR_3bit(regname):
10 return regname in ['BF', 'BFA']
12 def is_CR_5bit(regname):
13 return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
15 def is_GPR(regname):
16 return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
18 def get_regtype(regname):
19 if is_CR_3bit(regname):
20 return "CR_3bit"
21 if is_CR_5bit(regname):
22 return "CR_5bit"
23 if is_GPR(regname):
24 return "GPR"
27 def decode_extra(rm, prefix=''):
28 # first turn the svp64 rm into a "by name" dict, recording
29 # which position in the RM EXTRA it goes into
30 # also: record if the src or dest was a CR, for sanity-checking
31 # (elwidth overrides on CRs are banned)
32 dest_reg_cr, src_reg_cr = False, False
33 svp64_srcreg_byname = {}
34 svp64_destreg_byname = {}
35 for i in range(4):
36 print (rm)
37 rfield = rm[prefix+str(i)]
38 if not rfield or rfield == '0':
39 continue
40 print ("EXTRA field", i, rfield)
41 rfield = rfield.split(";") # s:RA;d:CR1 etc.
42 for r in rfield:
43 rtype = r[0]
44 # TODO: ignoring s/d makes it impossible to do
45 # LD/ST-with-update.
46 r = r[2:] # ignore s: and d:
47 if rtype == 'd':
48 svp64_destreg_byname[r] = i # dest reg in EXTRA position 0-3
49 else:
50 svp64_srcreg_byname[r] = i # src reg in EXTRA position 0-3
51 # check the regtype (if CR, record that)
52 regtype = get_regtype(r)
53 if regtype in ['CR_3bit', 'CR_5bit']:
54 if rtype == 'd':
55 dest_reg_cr = True
56 if rtype == 's':
57 src_reg_cr = True
59 return dest_reg_cr, src_reg_cr, svp64_srcreg_byname, svp64_destreg_byname
62 # gets SVP64 ReMap information
63 class SVP64RM:
64 def __init__(self, microwatt_format=False):
65 """SVP64RM: gets micro-opcode information
67 microwatt_format: moves RS to in1 (to match decode1.vhdl)
68 """
69 self.instrs = {}
70 self.svp64_instrs = {}
71 pth = find_wiki_dir()
72 for fname in os.listdir(pth):
73 if fname.startswith("RM") or fname.startswith("LDSTRM"):
74 for entry in get_csv(fname):
75 if microwatt_format:
76 # move RS from position 1 to position 3, to match
77 # microwatt decode1.vhdl format
78 if entry['in1'] == 'RS' and entry['in3'] == 'NONE':
79 entry['in1'] = 'NONE'
80 entry['in3'] = 'RS'
81 self.instrs[entry['insn']] = entry
84 def get_svp64_csv(self, fname):
85 # first get the v3.0B entries
86 v30b = get_csv(fname)
88 # now add the RM fields (for each instruction)
89 for entry in v30b:
90 # *sigh* create extra field "out2" based on LD/ST update
91 entry['out2'] = 'NONE'
92 if entry['upd'] == '1':
93 entry['out2'] = 'RA'
94 # dummy (blank) fields, first
95 entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
96 'EXTRA3': '0',
97 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
98 'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
99 for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
100 entry['sv_%s' % fname] = 'NONE'
102 # is this SVP64-augmented?
103 asmcode = entry['comment']
104 if asmcode not in self.instrs:
105 continue
107 # start updating the fields, merge relevant info
108 svp64 = self.instrs[asmcode]
109 for k, v in {'EXTRA0': '0', 'EXTRA1': '1', 'EXTRA2': '2',
110 'EXTRA3': '3',
111 'SV_Ptype': 'Ptype', 'SV_Etype': 'Etype'}.items():
112 entry[k] = svp64[v]
114 # hmm, we need something more useful: a cross-association
115 # of the in1/2/3 and CR in/out with the EXTRA0-3 fields
116 decode = decode_extra(entry, "EXTRA")
117 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
119 # now examine in1/2/3/out, create sv_in1/2/3/out
120 for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
121 regfield = entry[fname]
122 extra_index = None
123 if regfield == 'RA_OR_ZERO':
124 regfield = 'RA'
125 print (asmcode, regfield, fname, svp64_dest, svp64_src)
126 # find the reg in the SVP64 extra map
127 if (fname in ['out', 'out2'] and regfield in svp64_dest):
128 extra_index = svp64_dest[regfield]
129 if (fname not in ['out', 'out2'] and regfield in svp64_src):
130 extra_index = svp64_src[regfield]
131 # ta-daa, we know in1/2/3/out's bit-offset
132 if extra_index is not None:
133 entry['sv_%s' % fname] = "Idx"+str(extra_index)
135 # TODO: CRs a little tricky, the power_enums.CRInSel is a bit odd.
136 # ignore WHOLE_REG for now
137 cr_in = entry['CR in']
138 extra_index = 'NONE'
139 if cr_in in svp64_src:
140 entry['sv_cr_in'] = "Idx"+str(svp64_src[cr_in])
141 elif cr_in == 'BA_BB':
142 index1 = svp64_src.get('BA', None)
143 index2 = svp64_src.get('BB', None)
144 entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
146 # CRout a lot easier. ignore WHOLE_REG for now
147 cr_out = entry['CR out']
148 extra_index = svp64_dest.get(cr_out, None)
149 if extra_index is not None:
150 entry['sv_cr_out'] = 'Idx%d' % extra_index
152 # more enum-friendly Ptype names. should have done this in
153 # sv_analysis.py, oh well
154 if entry['SV_Ptype'] == '1P':
155 entry['SV_Ptype'] = 'P1'
156 if entry['SV_Ptype'] == '2P':
157 entry['SV_Ptype'] = 'P2'
158 self.svp64_instrs[asmcode] = entry
160 return v30b
162 if __name__ == '__main__':
163 isa = SVP64RM()
164 minor_31 = isa.get_svp64_csv("minor_31.csv")
165 for entry in minor_31:
166 if entry['comment'].startswith('ldu'):
167 print ("entry", entry)
168 minor_19 = isa.get_svp64_csv("minor_19.csv")
169 for entry in minor_19:
170 if entry['comment'].startswith('cr'):
171 print (entry)
172 minor_31 = isa.get_svp64_csv("minor_31.csv")
173 for entry in minor_31:
174 print (entry)