2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
5 from soc.decoder.power_enums import get_csv, find_wiki_dir
6 import os
8 # identifies register by type
9 def is_CR_3bit(regname):
10 return regname in ['BF', 'BFA']
12 def is_CR_5bit(regname):
13 return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
15 def is_GPR(regname):
16 return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
18 def get_regtype(regname):
19 if is_CR_3bit(regname):
20 return "CR_3bit"
21 if is_CR_5bit(regname):
22 return "CR_5bit"
23 if is_GPR(regname):
24 return "GPR"
27 def decode_extra(rm, prefix=''):
28 # first turn the svp64 rm into a "by name" dict, recording
29 # which position in the RM EXTRA it goes into
30 # also: record if the src or dest was a CR, for sanity-checking
31 # (elwidth overrides on CRs are banned)
32 dest_reg_cr, src_reg_cr = False, False
33 svp64_srcreg_byname = {}
34 svp64_destreg_byname = {}
35 for i in range(4):
36 print (rm)
37 rfield = rm[prefix+str(i)]
38 if not rfield or rfield == '0':
39 continue
40 print ("EXTRA field", i, rfield)
41 rfield = rfield.split(";") # s:RA;d:CR1 etc.
42 for r in rfield:
43 rtype = r[0]
44 # TODO: ignoring s/d makes it impossible to do
45 # LD/ST-with-update.
46 r = r[2:] # ignore s: and d:
47 if rtype == 'd':
48 svp64_destreg_byname[r] = i # dest reg in EXTRA position 0-3
49 else:
50 svp64_srcreg_byname[r] = i # src reg in EXTRA position 0-3
51 # check the regtype (if CR, record that)
52 regtype = get_regtype(r)
53 if regtype in ['CR_3bit', 'CR_5bit']:
54 if rtype == 'd':
55 dest_reg_cr = True
56 if rtype == 's':
57 src_reg_cr = True
59 return dest_reg_cr, src_reg_cr, svp64_srcreg_byname, svp64_destreg_byname
62 # gets SVP64 ReMap information
63 class SVP64RM:
64 def __init__(self):
65 self.instrs = {}
66 pth = find_wiki_dir()
67 for fname in os.listdir(pth):
68 if fname.startswith("RM") or fname.startswith("LDSTRM"):
69 for entry in get_csv(fname):
70 self.instrs[entry['insn']] = entry
73 def get_svp64_csv(self, fname):
74 # first get the v3.0B entries
75 v30b = get_csv(fname)
77 # now add the RM fields (for each instruction)
78 for entry in v30b:
79 # dummy (blank) fields, first
80 entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
81 'EXTRA3': '0',
82 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
83 'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
84 for fname in ['in1', 'in2', 'in3', 'out']:
85 entry['sv_%s' % fname] = 'NONE'
87 # is this SVP64-augmented?
88 asmcode = entry['comment']
89 if asmcode not in self.instrs:
90 continue
92 # start updating the fields, merge relevant info
93 svp64 = self.instrs[asmcode]
94 for k, v in {'EXTRA0': '0', 'EXTRA1': '1', 'EXTRA2': '2',
95 'EXTRA3': '3',
96 'SV_Ptype': 'Ptype', 'SV_Etype': 'Etype'}.items():
97 entry[k] = svp64[v]
99 # hmm, we need something more useful: a cross-association
100 # of the in1/2/3 and CR in/out with the EXTRA0-3 fields
101 decode = decode_extra(entry, "EXTRA")
102 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
104 # now examine in1/2/3/out, create sv_in1/2/3/out
105 for fname in ['in1', 'in2', 'in3', 'out']:
106 regfield = entry[fname]
107 extra_index = None
108 if regfield == 'RA_OR_ZERO':
109 regfield = 'RA'
110 print (asmcode, regfield, fname, svp64_dest, svp64_src)
111 # find the reg in the SVP64 extra map
112 if (fname == 'out' and regfield in svp64_dest):
113 extra_index = svp64_dest[regfield]
114 if (fname != 'out' and regfield in svp64_src):
115 extra_index = svp64_src[regfield]
116 # ta-daa, we know in1/2/3/out's bit-offset
117 if extra_index is not None:
118 entry['sv_%s' % fname] = "Idx"+str(extra_index)
120 # TODO: CRs a little tricky, the power_enums.CRInSel is a bit odd.
121 # ignore WHOLE_REG for now
122 cr_in = entry['CR in']
123 extra_index = 'NONE'
124 if cr_in in svp64_src:
125 entry['sv_cr_in'] = "Idx"+str(svp64_src[cr_in])
126 elif cr_in == 'BA_BB':
127 index1 = svp64_src.get('BA', None)
128 index2 = svp64_src.get('BB', None)
129 entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
131 # CRout a lot easier. ignore WHOLE_REG for now
132 cr_out = entry['CR out']
133 extra_index = svp64_dest.get(cr_out, None)
134 if extra_index is not None:
135 entry['sv_cr_out'] = 'Idx%d' % extra_index
137 # more enum-friendly Ptype names. should have done this in
138 # sv_analysis.py, oh well
139 if entry['SV_Ptype'] == '1P':
140 entry['SV_Ptype'] = 'P1'
141 if entry['SV_Ptype'] == '2P':
142 entry['SV_Ptype'] = 'P2'
144 return v30b
146 if __name__ == '__main__':
147 isa = SVP64RM()
148 minor_30 = isa.get_svp64_csv("minor_30.csv")
149 for entry in minor_30:
150 print (entry)
151 minor_19 = isa.get_svp64_csv("minor_19.csv")
152 for entry in minor_19:
153 if entry['comment'].startswith('cr'):
154 print (entry)
155 minor_31 = isa.get_svp64_csv("minor_31.csv")
156 for entry in minor_31:
157 print (entry)