1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_enums
import (Function
, MicrOp
,
9 In1Sel
, In2Sel
, In3Sel
,
11 OutSel
, RC
, LdstLen
, CryIn
,
13 get_signal_name
, get_csv
)
16 class DecoderTestCase(FHDLTestCase
):
18 def run_tst(self
, bitsel
, csvname
, minor
=None, suffix
=None, opint
=True):
22 function_unit
= Signal(Function
)
23 internal_op
= Signal(MicrOp
)
24 in1_sel
= Signal(In1Sel
)
25 in2_sel
= Signal(In2Sel
)
26 in3_sel
= Signal(In3Sel
)
27 out_sel
= Signal(OutSel
)
28 cr_in
= Signal(CRInSel
)
29 cr_out
= Signal(CROutSel
)
31 ldst_len
= Signal(LdstLen
)
32 cry_in
= Signal(CryIn
)
34 comb
+= bigendian
.eq(1)
36 # opcodes = get_csv(csvname)
37 m
.submodules
.dut
= dut
= create_pdecode()
38 comb
+= [dut
.raw_opcode_in
.eq(opcode
),
39 dut
.bigendian
.eq(bigendian
),
40 function_unit
.eq(dut
.op
.function_unit
),
41 in1_sel
.eq(dut
.op
.in1_sel
),
42 in2_sel
.eq(dut
.op
.in2_sel
),
43 in3_sel
.eq(dut
.op
.in3_sel
),
44 out_sel
.eq(dut
.op
.out_sel
),
45 cr_in
.eq(dut
.op
.cr_in
),
46 cr_out
.eq(dut
.op
.cr_out
),
47 rc_sel
.eq(dut
.op
.rc_sel
),
48 ldst_len
.eq(dut
.op
.ldst_len
),
49 cry_in
.eq(dut
.op
.cry_in
),
50 internal_op
.eq(dut
.op
.internal_op
)]
53 opcodes
= get_csv(csvname
)
60 if not opint
: # HACK: convert 001---10 to 0b00100010
61 op
= "0b" + op
.replace('-', '0')
62 print ("opint", opint
, row
['opcode'], op
)
65 yield opcode
[bitsel
[0]:bitsel
[1]].eq(int(op
, 0))
69 yield opcode
[minorbits
[0]:minorbits
[1]].eq(minor
[0])
71 # OR 0, 0, 0 ; 0x60000000 is decoded as a NOP
72 # If we're testing the OR instruction, make sure
73 # that the instruction is not 0x60000000
75 yield opcode
[24:25].eq(0b11)
78 signals
= [(function_unit
, Function
, 'unit'),
79 (internal_op
, MicrOp
, 'internal op'),
80 (in1_sel
, In1Sel
, 'in1'),
81 (in2_sel
, In2Sel
, 'in2'),
82 (in3_sel
, In3Sel
, 'in3'),
83 (out_sel
, OutSel
, 'out'),
84 (cr_in
, CRInSel
, 'CR in'),
85 (cr_out
, CROutSel
, 'CR out'),
87 (cry_in
, CryIn
, 'cry in'),
88 (ldst_len
, LdstLen
, 'ldst len')]
89 for sig
, enm
, name
in signals
:
91 expected
= enm
[row
[name
]]
92 msg
= f
"{sig.name} == {enm(result)}, expected: {expected}"
93 self
.assertEqual(enm(result
), expected
, msg
)
94 for bit
in single_bit_flags
:
95 sig
= getattr(dut
.op
, get_signal_name(bit
))
97 expected
= int(row
[bit
])
98 msg
= f
"{sig.name} == {result}, expected: {expected}"
99 self
.assertEqual(expected
, result
, msg
)
100 sim
.add_process(process
)
101 prefix
= os
.path
.splitext(csvname
)[0]
102 with sim
.write_vcd("%s.vcd" % prefix
, "%s.gtkw" % prefix
, traces
=[
103 opcode
, function_unit
, internal_op
,
107 def generate_ilang(self
):
108 pdecode
= create_pdecode()
109 vl
= rtlil
.convert(pdecode
, ports
=pdecode
.ports())
110 with
open("decoder.il", "w") as f
:
113 def test_major(self
):
114 self
.run_tst((26, 32), "major.csv")
115 self
.generate_ilang()
117 def test_minor_19(self
):
118 self
.run_tst((1, 11), "minor_19.csv", minor
=(19, (26, 32)),
121 # def test_minor_19_00000(self):
122 # self.run_tst((1, 11), "minor_19_00000.csv")
124 def test_minor_30(self
):
125 self
.run_tst((1, 5), "minor_30.csv", minor
=(30, (26, 32)))
127 def test_minor_31(self
):
128 self
.run_tst((1, 11), "minor_31.csv", minor
=(31, (26, 32)))
130 def test_minor_58(self
):
131 self
.run_tst((0, 2), "minor_58.csv", minor
=(58, (26, 32)))
133 def test_minor_62(self
):
134 self
.run_tst((0, 2), "minor_62.csv", minor
=(62, (26, 32)))
137 # #def test_minor_31_prefix(self):
138 # # self.run_tst(10, "minor_31.csv", suffix=(5, 10))
140 # def test_extra(self):
141 # self.run_tst(32, "extra.csv", opint=False)
142 # self.generate_ilang(32, "extra.csv", opint=False)
145 if __name__
== "__main__":