src/soc/experiment/compalu.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6 from soc.decoder.power_decoder2 import Data
   7 from soc.decoder.power_enums import InternalOp
   8
   9 from alu_hier import CompALUOpSubset
  10
  11 """ Computation Unit (aka "ALU Manager").
  12
  13     This module runs a "revolving door" set of three latches, based on
  14     * Issue
  15     * Go_Read
  16     * Go_Write
  17     where one of them cannot be set on any given cycle.
  18     (Note however that opc_l has been inverted (and qn used), due to SRLatch
  19      default reset state being "0" rather than "1")
  20
  21     * When issue is first raised, a busy signal is sent out.
  22       The src1 and src2 registers and the operand can be latched in
  23       at this point
  24
  25     * Read request is set, which is acknowledged through the Scoreboard
  26       to the priority picker, which generates (one and only one) Go_Read
  27       at a time.  One of those will (eventually) be this Computation Unit.
  28
  29     * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
  30       src1/src2/operand in place), and the ALU is told to proceed.
  31
  32     * As this is currently a "demo" unit, a countdown timer is activated
  33       to simulate an ALU "pipeline", which activates "write request release",
  34       and the ALU's output is captured into a temporary register.
  35
  36     * Write request release will go through a similar process as Read request,
  37       resulting (eventually) in Go_Write being asserted.
  38
  39     * When Go_Write is asserted, two things happen: (1) the data in the temp
  40       register is placed combinatorially onto the output, and (2) the
  41       req_l latch is cleared, busy is dropped, and the Comp Unit is back
  42       through its revolving door to do another task.
  43 """
  44
  45
  46 class ComputationUnitNoDelay(Elaboratable):
  47     def __init__(self, rwid, alu):
  48         self.rwid = rwid
  49         self.alu = alu # actual ALU - set as a "submodule" of the CU
  50
  51         self.counter = Signal(4)
  52         self.go_rd_i = Signal(reset_less=True) # go read in
  53         self.go_wr_i = Signal(reset_less=True) # go write in
  54         self.issue_i = Signal(reset_less=True) # fn issue in
  55         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  56         self.go_die_i = Signal() # go die (reset)
  57
  58         # operation / data input
  59         self.oper_i = CompALUOpSubset() # operand
  60         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  61         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  62
  63         self.busy_o = Signal(reset_less=True) # fn busy out
  64         self.data_o = Signal(rwid, reset_less=True) # Dest out
  65         self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
  66         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
  67         self.done_o = self.req_rel_o # 'normalise' API
  68
  69     def elaborate(self, platform):
  70         m = Module()
  71         m.submodules.alu = self.alu
  72         m.submodules.src_l = src_l = SRLatch(sync=False, name="src")
  73         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
  74         m.submodules.req_l = req_l = SRLatch(sync=False, name="req")
  75
  76         # shadow/go_die
  77         reset_w = Signal(reset_less=True)
  78         reset_r = Signal(reset_less=True)
  79         m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
  80         m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
  81
  82         # This is fascinating and very important to observe that this
  83         # is in effect a "3-way revolving door".  At no time may all 3
  84         # latches be set at the same time.
  85
  86         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
  87         m.d.sync += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
  88         m.d.sync += opc_l.r.eq(reset_w)      # XXX NOTE: INVERTED FROM book!
  89
  90         # src operand latch (not using go_wr_i)
  91         m.d.sync += src_l.s.eq(self.issue_i)
  92         m.d.sync += src_l.r.eq(reset_r)
  93
  94         # dest operand latch (not using issue_i)
  95         m.d.sync += req_l.s.eq(self.go_rd_i)
  96         m.d.sync += req_l.r.eq(reset_w)
  97
  98         # create a latch/register for the operand
  99         oper_r = CompALUOpSubset()
 100         latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
 101
 102         # and one for the output from the ALU
 103         data_r = Signal(self.rwid, reset_less=True) # Dest register
 104         latchregister(m, self.alu.o, data_r, req_l.q, "data_r")
 105
 106         # pass the operation to the ALU
 107         m.d.comb += self.alu.op.eq(oper_r)
 108
 109         # select immediate if opcode says so.  however also change the latch
 110         # to trigger *from* the opcode latch instead.
 111         op_is_imm = oper_r.imm_data.imm_ok
 112         src2_or_imm = Signal(self.rwid, reset_less=True)
 113         src_sel = Signal(reset_less=True)
 114         m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.q, src_l.q))
 115         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm,
 116                                                   self.src2_i))
 117
 118         # create a latch/register for src1/src2
 119         latchregister(m, self.src1_i, self.alu.a, src_l.q)
 120         latchregister(m, src2_or_imm, self.alu.b, src_sel)
 121
 122         # -----
 123         # outputs
 124         # -----
 125
 126         # all request signals gated by busy_o.  prevents picker problems
 127         busy_o = self.busy_o
 128         m.d.comb += busy_o.eq(opc_l.q) # busy out
 129         m.d.comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
 130
 131         # on a go_read, tell the ALU we're accepting data.
 132         # NOTE: this spells TROUBLE if the ALU isn't ready!
 133         # go_read is only valid for one clock!
 134         with m.If(self.go_rd_i):                     # src operands ready, GO!
 135             with m.If(~self.alu.p_ready_o):          # no ACK yet
 136                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 137
 138         # only proceed if ALU says its output is valid
 139         with m.If(self.alu.n_valid_o):
 140             # when ALU ready, write req release out. waits for shadow
 141             m.d.comb += self.req_rel_o.eq(req_l.q & busy_o & self.shadown_i)
 142             # when output latch is ready, and ALU says ready, accept ALU output
 143             with m.If(self.req_rel_o & self.go_wr_i):
 144                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 145
 146         # output the data from the latch on go_write
 147         with m.If(self.go_wr_i):
 148             m.d.comb += self.data_o.eq(data_r)
 149
 150         return m
 151
 152     def __iter__(self):
 153         yield self.go_rd_i
 154         yield self.go_wr_i
 155         yield self.issue_i
 156         yield self.shadown_i
 157         yield self.go_die_i
 158         yield from self.oper_i.ports()
 159         yield self.src1_i
 160         yield self.src2_i
 161         yield self.busy_o
 162         yield self.rd_rel_o
 163         yield self.req_rel_o
 164         yield self.data_o
 165
 166     def ports(self):
 167         return list(self)
 168
 169
 170 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0):
 171     yield dut.issue_i.eq(0)
 172     yield
 173     yield dut.src1_i.eq(a)
 174     yield dut.src2_i.eq(b)
 175     yield dut.oper_i.insn_type.eq(op)
 176     yield dut.oper_i.invert_a.eq(inv_a)
 177     yield dut.oper_i.imm_data.imm.eq(imm)
 178     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 179     yield dut.issue_i.eq(1)
 180     yield
 181     yield dut.issue_i.eq(0)
 182     yield
 183     yield dut.go_rd_i.eq(1)
 184     while True:
 185         yield
 186         rd_rel_o = yield dut.rd_rel_o
 187         print ("rd_rel", rd_rel_o)
 188         if rd_rel_o:
 189             break
 190     yield
 191     yield dut.go_rd_i.eq(0)
 192     req_rel_o = yield dut.req_rel_o
 193     result = yield dut.data_o
 194     print ("req_rel", req_rel_o, result)
 195     while True:
 196         req_rel_o = yield dut.req_rel_o
 197         result = yield dut.data_o
 198         print ("req_rel", req_rel_o, result)
 199         if req_rel_o:
 200             break
 201         yield
 202     yield dut.go_wr_i.eq(1)
 203     yield
 204     result = yield dut.data_o
 205     print ("result", result)
 206     yield dut.go_wr_i.eq(0)
 207     yield
 208     return result
 209
 210
 211 def scoreboard_sim(dut):
 212     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=0,
 213                                     imm=8, imm_ok=1)
 214     assert result == 13
 215
 216     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD, inv_a=1)
 217     assert result == 65532
 218
 219     result = yield from op_sim(dut, 5, 2, InternalOp.OP_ADD)
 220     assert result == 7
 221
 222
 223 def test_scoreboard():
 224     from alu_hier import ALU
 225     from soc.decoder.power_decoder2 import Decode2ToExecute1Type
 226
 227     alu = ALU(16)
 228     dut = ComputationUnitNoDelay(16, alu)
 229     vl = rtlil.convert(dut, ports=dut.ports())
 230     with open("test_compalu.il", "w") as f:
 231         f.write(vl)
 232
 233     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_compalu.vcd')
 234
 235 if __name__ == '__main__':
 236     test_scoreboard()