src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 Both LD and ST may request that the address be computed from summing
  24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25 the immediate (from the opcode).
  26
  27 Both LD and ST may also request "update" mode (op_is_update) which
  28 activates the use of Go_Write[1] to control storage of the EA into
  29 a *second* operand in the register file.
  30
  31 Thus this module has *TWO* write-requests to the register file and
  32 *THREE* read-requests to the register file (not all at the same time!)
  33 The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47 the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59 Full diagram:
  60
  61     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  62
  63 Links including to walk-through videos:
  64
  65     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  66     * http://libre-soc.org/openpower/isa/fixedload
  67     * http://libre-soc.org/openpower/isa/fixedstore
  68
  69 Related Bugreports:
  70
  71     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  72     * https://bugs.libre-soc.org/show_bug.cgi?id=216
  73
  74 Terminology:
  75
  76     * EA - Effective Address
  77     * LD - Load
  78     * ST - Store
  79 """
  80
  81 from nmigen.compat.sim import run_simulation
  82 from nmigen.cli import verilog, rtlil
  83 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  84 from nmigen.hdl.rec import Record, Layout
  85
  86 from nmutil.latch import SRLatch, latchregister
  87 from nmutil.byterev import byte_reverse
  88
  89 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  90 from soc.experiment.l0_cache import PortInterface
  91 from soc.fu.regspec import RegSpecAPI
  92
  93 from soc.decoder.power_enums import MicrOp, Function, LDSTMode
  94 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  95 from soc.decoder.power_decoder2 import Data
  96
  97
  98 class LDSTCompUnitRecord(CompUnitRecord):
  99     def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
 100         CompUnitRecord.__init__(self, opsubset, rwid,
 101                                 n_src=3, n_dst=2, name=name)
 102
 103         self.ad = go_record(1, name="cu_ad")  # address go in, req out
 104         self.st = go_record(1, name="cu_st")  # store go in, req out
 105
 106         self.addr_exc_o = Signal(reset_less=True)   # address exception
 107
 108         self.ld_o = Signal(reset_less=True)  # operation is a LD
 109         self.st_o = Signal(reset_less=True)  # operation is a ST
 110
 111         # hmm... are these necessary?
 112         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 113         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 114
 115
 116 class LDSTCompUnit(RegSpecAPI, Elaboratable):
 117     """LOAD / STORE Computation Unit
 118
 119     Inputs
 120     ------
 121
 122     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 123     * :rwid:   register width
 124     * :awid:   address width
 125
 126     Data inputs
 127     -----------
 128     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 129
 130     Data (outputs)
 131     --------------
 132     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 133     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 134     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 135
 136     TODO: make addr_exc_o a data-type rather than a single-bit signal
 137           (see bug #302)
 138
 139     Control Signals (In)
 140     --------------------
 141
 142     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 143     * :issue_i:    LD/ST is being "issued".
 144     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 145     * :go_rd_i:    read is being actioned (latches in src regs)
 146     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 147     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 148     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 149     * :go_die_i:   resets the unit back to "wait for issue"
 150
 151     Control Signals (Out)
 152     ---------------------
 153
 154     * :busy_o:      function unit is busy
 155     * :rd_rel_o:    request src1/src2
 156     * :adr_rel_o:   request address (from mem)
 157     * :sto_rel_o:   request store (to mem)
 158     * :req_rel_o:   request write (result)
 159     * :load_mem_o:  activate memory LOAD
 160     * :stwd_mem_o:  activate memory STORE
 161
 162     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 163     in a single cycle and the CompUnit set back to doing another op.
 164     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 165     depending on whether the operation is a ST or LD.
 166
 167     Note: LDSTCompUnit takes care of LE/BE normalisation:
 168     * LD data is normalised after receipt from the PortInterface
 169     * ST data is normalised *prior* to sending onto the PortInterface
 170     TODO: use one module for the byte-reverse as it's quite expensive in gates
 171     """
 172
 173     def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
 174                  debugtest=False, name=None):
 175         super().__init__(rwid)
 176         self.awid = awid
 177         self.pi = pi
 178         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
 179         self.debugtest = debugtest
 180
 181         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 182         self.n_src = n_src = 3   # RA, RB, RT/RS
 183         self.n_dst = n_dst = 2  # RA, RT/RS
 184
 185         # set up array of src and dest signals
 186         for i in range(n_src):
 187             j = i + 1  # name numbering to match src1/src2
 188             name = "src%d_i" % j
 189             setattr(self, name, getattr(cu, name))
 190
 191         dst = []
 192         for i in range(n_dst):
 193             j = i + 1  # name numbering to match dest1/2...
 194             name = "dest%d_o" % j
 195             setattr(self, name, getattr(cu, name))
 196
 197         # convenience names
 198         self.rd = cu.rd
 199         self.wr = cu.wr
 200         self.rdmaskn = cu.rdmaskn
 201         self.wrmask = cu.wrmask
 202         self.ad = cu.ad
 203         self.st = cu.st
 204         self.dest = cu._dest
 205
 206         # HACK: get data width from dest[0].  this is used across the board
 207         # (it really shouldn't be)
 208         self.data_wid = self.dest[0].shape()
 209
 210         self.go_rd_i = self.rd.go_i  # temporary naming
 211         self.go_wr_i = self.wr.go_i  # temporary naming
 212         self.go_ad_i = self.ad.go_i  # temp naming: go address in
 213         self.go_st_i = self.st.go_i  # temp naming: go store in
 214
 215         self.rd_rel_o = self.rd.rel_o  # temporary naming
 216         self.req_rel_o = self.wr.rel_o  # temporary naming
 217         self.adr_rel_o = self.ad.rel_o  # request address (from mem)
 218         self.sto_rel_o = self.st.rel_o  # request store (to mem)
 219
 220         self.issue_i = cu.issue_i
 221         self.shadown_i = cu.shadown_i
 222         self.go_die_i = cu.go_die_i
 223
 224         self.oper_i = cu.oper_i
 225         self.src_i = cu._src_i
 226
 227         self.data_o = Data(self.data_wid, name="o")  # Dest1 out: RT
 228         self.addr_o = Data(self.data_wid, name="ea")  # Addr out: Update => RA
 229         self.addr_exc_o = cu.addr_exc_o
 230         self.done_o = cu.done_o
 231         self.busy_o = cu.busy_o
 232
 233         self.ld_o = cu.ld_o
 234         self.st_o = cu.st_o
 235
 236         self.load_mem_o = cu.load_mem_o
 237         self.stwd_mem_o = cu.stwd_mem_o
 238
 239     def elaborate(self, platform):
 240         m = Module()
 241
 242         # temp/convenience
 243         comb = m.d.comb
 244         sync = m.d.sync
 245         issue_i = self.issue_i
 246
 247         #####################
 248         # latches for the FSM.
 249         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 250         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 251         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 252         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 253         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 254         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 255         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 256         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 257         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 258         m.submodules.lsd_l = lsd_l = SRLatch(sync=False, name="lsd") # done
 259
 260         ####################
 261         # signals
 262
 263         # opcode decode
 264         op_is_ld = Signal(reset_less=True)
 265         op_is_st = Signal(reset_less=True)
 266
 267         # ALU/LD data output control
 268         alu_valid = Signal(reset_less=True)  # ALU operands are valid
 269         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 270         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 271         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 272         wr_any = Signal(reset_less=True)    # any write (incl. store)
 273         rda_any = Signal(reset_less=True)   # any read for address ops
 274         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 275         wr_reset = Signal(reset_less=True)  # final reset condition
 276
 277         # LD and ALU out
 278         alu_o = Signal(self.data_wid, reset_less=True)
 279         ldd_o = Signal(self.data_wid, reset_less=True)
 280
 281         ##############################
 282         # reset conditions for latches
 283
 284         # temporaries (also convenient when debugging)
 285         reset_o = Signal(reset_less=True)             # reset opcode
 286         reset_w = Signal(reset_less=True)             # reset write
 287         reset_u = Signal(reset_less=True)             # reset update
 288         reset_a = Signal(reset_less=True)             # reset adr latch
 289         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 290         reset_r = Signal(self.n_src, reset_less=True)  # reset src
 291         reset_s = Signal(reset_less=True)             # reset store
 292
 293         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 294         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 295         comb += reset_w.eq(self.wr.go_i[0] | self.go_die_i)  # write reg 1
 296         comb += reset_u.eq(self.wr.go_i[1] | self.go_die_i)  # update (reg 2)
 297         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 298         comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
 299         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 300
 301         p_st_go = Signal(reset_less=True)
 302         sync += p_st_go.eq(self.st.go_i)
 303
 304         ##########################
 305         # FSM implemented through sequence of latches.  approximately this:
 306         # - opc_l       : opcode
 307         #    - src_l[0] : operands
 308         #    - src_l[1]
 309         #       - alu_l : looks after add of src1/2/imm (EA)
 310         #       - adr_l : waits for add (EA)
 311         #       - upd_l : waits for adr and Regfile (port 2)
 312         #    - src_l[2] : ST
 313         # - lod_l       : waits for adr (EA) and for LD Data
 314         # - wri_l       : waits for LD Data and Regfile (port 1)
 315         # - st_l        : waits for alu and operand2
 316         # - rst_l       : waits for all FSM paths to converge.
 317         # NOTE: use sync to stop combinatorial loops.
 318
 319         # opcode latch - inverted so that busy resets to 0
 320         # note this MUST be sync so as to avoid a combinatorial loop
 321         # between busy_o and issue_i on the reset latch (rst_l)
 322         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 323         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 324
 325         # src operand latch
 326         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 327         sync += src_l.r.eq(reset_r)
 328
 329         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 330         comb += alu_l.s.eq(reset_i)
 331         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 332
 333         # addr latch
 334         comb += adr_l.s.eq(reset_i)
 335         sync += adr_l.r.eq(reset_a)
 336
 337         # ld latch
 338         comb += lod_l.s.eq(reset_i)
 339         comb += lod_l.r.eq(ld_ok)
 340
 341         # dest operand latch
 342         comb += wri_l.s.eq(issue_i)
 343         sync += wri_l.r.eq(reset_w | Repl(self.done_o, self.n_dst))
 344
 345         # update-mode operand latch (EA written to reg 2)
 346         sync += upd_l.s.eq(reset_i)
 347         sync += upd_l.r.eq(reset_u)
 348
 349         # store latch
 350         comb += sto_l.s.eq(addr_ok & op_is_st)
 351         sync += sto_l.r.eq(reset_s | p_st_go)
 352
 353         # ld/st done.  needed to stop LD/ST from activating repeatedly
 354         comb += lsd_l.s.eq(issue_i)
 355         sync += lsd_l.r.eq(reset_s | p_st_go | ld_ok)
 356
 357         # reset latch
 358         comb += rst_l.s.eq(addr_ok)  # start when address is ready
 359         comb += rst_l.r.eq(issue_i)
 360
 361         # create a latch/register for the operand
 362         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 363         with m.If(self.issue_i):
 364             sync += oper_r.eq(self.oper_i)
 365         with m.If(self.done_o):
 366             sync += oper_r.eq(0)
 367
 368         # and for LD
 369         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
 370         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 371
 372         # and for each input from the incoming src operands
 373         srl = []
 374         for i in range(self.n_src):
 375             name = "src_r%d" % i
 376             src_r = Signal(self.data_wid, name=name, reset_less=True)
 377             with m.If(self.rd.go_i[i]):
 378                 sync += src_r.eq(self.src_i[i])
 379             with m.If(self.issue_i):
 380                 sync += src_r.eq(0)
 381             srl.append(src_r)
 382
 383         # and one for the output from the ADD (for the EA)
 384         addr_r = Signal(self.data_wid, reset_less=True)  # Effective Address
 385         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 386
 387         # select either zero or src1 if opcode says so
 388         op_is_z = oper_r.zero_a
 389         src1_or_z = Signal(self.data_wid, reset_less=True)
 390         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 391
 392         # select either immediate or src2 if opcode says so
 393         op_is_imm = oper_r.imm_data.imm_ok
 394         src2_or_imm = Signal(self.data_wid, reset_less=True)
 395         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 396
 397         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 398         comb += alu_o.eq(src1_or_z + src2_or_imm)  # actual EA
 399         m.d.sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 400
 401         # decode bits of operand (latched)
 402         comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE)  # ST
 403         comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD)  # LD
 404         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
 405         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
 406         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 407         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 408         comb += self.ld_o.eq(op_is_ld)
 409         comb += self.st_o.eq(op_is_st)
 410
 411         ############################
 412         # Control Signal calculation
 413
 414         # busy signal
 415         busy_o = self.busy_o
 416         comb += self.busy_o.eq(opc_l.q)  # | self.pi.busy_o)  # busy out
 417
 418         # 1st operand read-request only when zero not active
 419         # 2nd operand only needed when immediate is not active
 420         slg = Cat(op_is_z, op_is_imm)
 421         bro = Repl(self.busy_o, self.n_src)
 422         comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
 423
 424         # note when the address-related read "go" signals are active
 425         comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
 426
 427         # alu input valid when 1st and 2nd ops done (or imm not active)
 428         comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
 429
 430         # 3rd operand only needed when operation is a store
 431         comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
 432
 433         # all reads done when alu is valid and 3rd operand needed
 434         comb += rd_done.eq(alu_valid & ~self.rd.rel_o[2])
 435
 436         # address release only if addr ready, but Port must be idle
 437         comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 438
 439         # store release when st ready *and* all operands read (and no shadow)
 440         comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
 441                                self.shadown_i)
 442
 443         # request write of LD result.  waits until shadow is dropped.
 444         comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
 445                                   op_is_ld & self.shadown_i)
 446
 447         # request write of EA result only in update mode
 448         comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
 449                                   alu_valid & self.shadown_i)
 450
 451         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 452         comb += wr_any.eq(self.st.go_i | p_st_go |
 453                           self.wr.go_i[0] | self.wr.go_i[1])
 454         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 455                             ~(self.st.rel_o | self.wr.rel_o[0] |
 456                               self.wr.rel_o[1]) &
 457                             (lod_l.qn | op_is_st) &
 458                             (~self.pi.busy_o | op_is_ld))
 459         comb += self.done_o.eq(wr_reset)
 460
 461         ######################
 462         # Data/Address outputs
 463
 464         # put the LD-output register directly onto the output bus on a go_write
 465         comb += self.data_o.data.eq(self.dest[0])
 466         with m.If(self.wr.go_i[0]):
 467             comb += self.dest[0].eq(ldd_r)
 468
 469         # "update" mode, put address out on 2nd go-write
 470         comb += self.addr_o.data.eq(self.dest[1])
 471         with m.If(op_is_update & self.wr.go_i[1]):
 472             comb += self.dest[1].eq(addr_r)
 473
 474         # need to look like MultiCompUnit: put wrmask out.
 475         # XXX may need to make this enable only when write active
 476         comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
 477
 478         ###########################
 479         # PortInterface connections
 480         pi = self.pi
 481
 482         # connect to LD/ST PortInterface.
 483         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 484         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 485         comb += pi.data_len.eq(oper_r.data_len)  # data_len
 486         # address: use sync to avoid long latency
 487         sync += pi.addr.data.eq(addr_r)           # EA from adder
 488         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
 489         comb += self.addr_exc_o.eq(pi.addr_exc_o)  # exception occurred
 490         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 491
 492         # byte-reverse on LD
 493         with m.If(oper_r.byte_reverse):
 494             # byte-reverse the data based on ld/st width (turn it to LE)
 495             data_len = oper_r.data_len
 496             lddata_r = byte_reverse(m, 'lddata_r', pi.ld.data, data_len)
 497             comb += ldd_o.eq(lddata_r)  # put reversed- data out
 498         with m.Else():
 499             comb += ldd_o.eq(pi.ld.data)  # put data out, straight (as BE)
 500         # ld - ld gets latched in via lod_l
 501         comb += ld_ok.eq(pi.ld.ok)  # ld.ok *closes* (freezes) ld data
 502
 503         # byte-reverse on ST
 504         op3 = srl[2] # 3rd operand latch
 505         with m.If(oper_r.byte_reverse):
 506             # byte-reverse the data based on width
 507             data_len = oper_r.data_len
 508             stdata_r = byte_reverse(m, 'stdata_r', op3, data_len)
 509             comb += pi.st.data.eq(stdata_r)
 510         with m.Else():
 511             comb += pi.st.data.eq(op3)
 512         # store - data goes in based on go_st
 513         comb += pi.st.ok.eq(self.st.go_i)  # go store signals st data valid
 514
 515         return m
 516
 517     def get_out(self, i):
 518         """make LDSTCompUnit look like RegSpecALUAPI"""
 519         if i == 0:
 520             return self.data_o
 521         if i == 1:
 522             return self.addr_o
 523         # return self.dest[i]
 524
 525     def get_fu_out(self, i):
 526         return self.get_out(i)
 527
 528     def __iter__(self):
 529         yield self.rd.go_i
 530         yield self.go_ad_i
 531         yield self.wr.go_i
 532         yield self.go_st_i
 533         yield self.issue_i
 534         yield self.shadown_i
 535         yield self.go_die_i
 536         yield from self.oper_i.ports()
 537         yield from self.src_i
 538         yield self.busy_o
 539         yield self.rd.rel_o
 540         yield self.adr_rel_o
 541         yield self.sto_rel_o
 542         yield self.wr.rel_o
 543         yield from self.data_o.ports()
 544         yield from self.addr_o.ports()
 545         yield self.load_mem_o
 546         yield self.stwd_mem_o
 547
 548     def ports(self):
 549         return list(self)
 550
 551
 552 def wait_for(sig, wait=True, test1st=False):
 553     v = (yield sig)
 554     print("wait for", sig, v, wait, test1st)
 555     if test1st and bool(v) == wait:
 556         return
 557     while True:
 558         yield
 559         v = (yield sig)
 560         #print("...wait for", sig, v)
 561         if bool(v) == wait:
 562             break
 563
 564
 565 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
 566           byterev=True):
 567     print("ST", src1, src2, src3, imm, imm_ok, update)
 568     yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)
 569     yield dut.oper_i.data_len.eq(2)  # half-word
 570     yield dut.oper_i.byte_reverse.eq(byterev)
 571     yield dut.src1_i.eq(src1)
 572     yield dut.src2_i.eq(src2)
 573     yield dut.src3_i.eq(src3)
 574     yield dut.oper_i.imm_data.imm.eq(imm)
 575     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 576     yield dut.oper_i.update.eq(update)
 577     yield dut.issue_i.eq(1)
 578     yield
 579     yield dut.issue_i.eq(0)
 580
 581     if imm_ok:
 582         active_rel = 0b101
 583     else:
 584         active_rel = 0b111
 585     # wait for all active rel signals to come up
 586     while True:
 587         rel = yield dut.rd.rel_o
 588         if rel == active_rel:
 589             break
 590         yield
 591     yield dut.rd.go.eq(active_rel)
 592     yield
 593     yield dut.rd.go.eq(0)
 594
 595     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 596     # yield from wait_for(dut.adr_rel_o)
 597     # yield dut.ad.go.eq(1)
 598     # yield
 599     # yield dut.ad.go.eq(0)
 600
 601     if update:
 602         yield from wait_for(dut.wr.rel_o[1])
 603         yield dut.wr.go.eq(0b10)
 604         yield
 605         addr = yield dut.addr_o
 606         print("addr", addr)
 607         yield dut.wr.go.eq(0)
 608     else:
 609         addr = None
 610
 611     yield from wait_for(dut.sto_rel_o)
 612     yield dut.go_st_i.eq(1)
 613     yield
 614     yield dut.go_st_i.eq(0)
 615     yield from wait_for(dut.busy_o, False)
 616     # wait_for(dut.stwd_mem_o)
 617     yield
 618     return addr
 619
 620
 621 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
 622          byterev=True):
 623     print("LD", src1, src2, imm, imm_ok, update)
 624     yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
 625     yield dut.oper_i.data_len.eq(2)  # half-word
 626     yield dut.oper_i.byte_reverse.eq(byterev)
 627     yield dut.src1_i.eq(src1)
 628     yield dut.src2_i.eq(src2)
 629     yield dut.oper_i.zero_a.eq(zero_a)
 630     yield dut.oper_i.imm_data.imm.eq(imm)
 631     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 632     yield dut.issue_i.eq(1)
 633     yield
 634     yield dut.issue_i.eq(0)
 635     yield
 636
 637     # set up read-operand flags
 638     rd = 0b00
 639     if not imm_ok:  # no immediate means RB register needs to be read
 640         rd |= 0b10
 641     if not zero_a:  # no zero-a means RA needs to be read
 642         rd |= 0b01
 643
 644     # wait for the operands (RA, RB, or both)
 645     if rd:
 646         yield dut.rd.go.eq(rd)
 647         yield from wait_for(dut.rd.rel_o)
 648         yield dut.rd.go.eq(0)
 649
 650     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 651     # yield dut.ad.go.eq(1)
 652     # yield
 653     # yield dut.ad.go.eq(0)
 654
 655     if update:
 656         yield from wait_for(dut.wr.rel_o[1])
 657         yield dut.wr.go.eq(0b10)
 658         yield
 659         addr = yield dut.addr_o
 660         print("addr", addr)
 661         yield dut.wr.go.eq(0)
 662     else:
 663         addr = None
 664
 665     yield from wait_for(dut.wr.rel_o[0], test1st=True)
 666     yield dut.wr.go.eq(1)
 667     yield
 668     data = yield dut.data_o
 669     print(data)
 670     yield dut.wr.go.eq(0)
 671     yield from wait_for(dut.busy_o)
 672     yield
 673     # wait_for(dut.stwd_mem_o)
 674     return data, addr
 675
 676
 677 def ldst_sim(dut):
 678
 679     ###################
 680     # immediate version
 681
 682     # two STs (different addresses)
 683     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 684     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 685     yield
 686     # two LDs (deliberately LD from the 1st address then 2nd)
 687     data, addr = yield from load(dut, 4, 0, 2)
 688     assert data == 0x0003, "returned %x" % data
 689     data, addr = yield from load(dut, 2, 0, 2)
 690     assert data == 0x0009, "returned %x" % data
 691     yield
 692
 693     # indexed version
 694     yield from store(dut, 9, 5, 3, 0, imm_ok=False)
 695     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
 696     assert data == 0x0003, "returned %x" % data
 697
 698     # update-immediate version
 699     addr = yield from store(dut, 9, 6, 3, 2, update=True)
 700     assert addr == 0x000b, "returned %x" % addr
 701
 702     # update-indexed version
 703     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
 704     assert data == 0x0003, "returned %x" % data
 705     assert addr == 0x000e, "returned %x" % addr
 706
 707     # immediate *and* zero version
 708     data, addr = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
 709     assert data == 0x0008, "returned %x" % data
 710
 711
 712 class TestLDSTCompUnit(LDSTCompUnit):
 713
 714     def __init__(self, rwid):
 715         from soc.experiment.l0_cache import TstL0CacheBuffer
 716         self.l0 = l0 = TstL0CacheBuffer()
 717         pi = l0.l0.dports[0].pi
 718         LDSTCompUnit.__init__(self, pi, rwid, 4)
 719
 720     def elaborate(self, platform):
 721         m = LDSTCompUnit.elaborate(self, platform)
 722         m.submodules.l0 = self.l0
 723         m.d.comb += self.ad.go.eq(self.ad.rel)  # link addr-go direct to rel
 724         return m
 725
 726
 727 def test_scoreboard():
 728
 729     dut = TestLDSTCompUnit(16)
 730     vl = rtlil.convert(dut, ports=dut.ports())
 731     with open("test_ldst_comp.il", "w") as f:
 732         f.write(vl)
 733
 734     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 735
 736
 737 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 738
 739     def __init__(self):
 740         from soc.experiment.l0_cache import TstL0CacheBuffer
 741         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 742         regspec = LDSTPipeSpec.regspec
 743         self.l0 = l0 = TstL0CacheBuffer()
 744         pi = l0.l0.dports[0].pi
 745         LDSTCompUnit.__init__(self, pi, regspec, 4)
 746
 747     def elaborate(self, platform):
 748         m = LDSTCompUnit.elaborate(self, platform)
 749         m.submodules.l0 = self.l0
 750         m.d.comb += self.ad.go.eq(self.ad.rel)  # link addr-go direct to rel
 751         return m
 752
 753
 754 def test_scoreboard_regspec():
 755
 756     dut = TestLDSTCompUnitRegSpec()
 757     vl = rtlil.convert(dut, ports=dut.ports())
 758     with open("test_ldst_comp.il", "w") as f:
 759         f.write(vl)
 760
 761     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 762
 763
 764 if __name__ == '__main__':
 765     test_scoreboard_regspec()
 766     test_scoreboard()