convert score6600_multi over to using RegSpecs (in a fake way)
[soc.git] / src / soc / experiment / compldst_multi.py
1 """LOAD / STORE Computation Unit.
2
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
8
9 ----
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
13 ----
14
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
18
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
22
23 TODO: dcbz, yes, that's going to be complicated, has to be done
24 with great care, to detect the case when dcbz is set
25 and *not* expect to read any data, just the address.
26 so, wait for RA but not RB.
27
28 Both LD and ST may request that the address be computed from summing
29 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
30 the immediate (from the opcode).
31
32 Both LD and ST may also request "update" mode (op_is_update) which
33 activates the use of Go_Write[1] to control storage of the EA into
34 a *second* operand in the register file.
35
36 Thus this module has *TWO* write-requests to the register file and
37 *THREE* read-requests to the register file (not all at the same time!)
38 The regfile port usage is:
39
40 * LD-imm 1R1W
41 * LD-imm-update 1R2W
42 * LD-idx 2R1W
43 * LD-idx-update 2R2W
44
45 * ST-imm 2R
46 * ST-imm-update 2R1W
47 * ST-idx 3R
48 * ST-idx-update 3R1W
49
50 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
51 is not suited to (nmigen.FSM is clock-driven, and some aspects of
52 the nested FSMs below are *combinatorial*).
53
54 * One FSM covers Operand collection and communication address-side
55 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
56
57 * A second FSM activates to cover LD. it activates if op_is_ld is true
58
59 * A third FSM activates to cover ST. it activates if op_is_st is true
60
61 * TODO document DCBZ (not complete yet)
62
63 * The "overall" (fourth) FSM coordinates the progression and completion
64 of the three other FSMs, firing "WR_RESET" which switches off "busy"
65
66 Full diagram:
67
68 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
69
70 Links including to walk-through videos:
71
72 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
73 * http://libre-soc.org/openpower/isa/fixedload
74 * http://libre-soc.org/openpower/isa/fixedstore
75
76 Related Bugreports:
77
78 * https://bugs.libre-soc.org/show_bug.cgi?id=302
79 * https://bugs.libre-soc.org/show_bug.cgi?id=216
80
81 Terminology:
82
83 * EA - Effective Address
84 * LD - Load
85 * ST - Store
86 """
87
88 from nmigen.compat.sim import run_simulation
89 from nmigen.cli import verilog, rtlil
90 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
91 from nmigen.hdl.rec import Record, Layout
92
93 from nmutil.latch import SRLatch, latchregister
94 from nmutil.byterev import byte_reverse
95 from nmutil.extend import exts
96
97 from soc.experiment.compalu_multi import go_record, CompUnitRecord
98 from soc.experiment.l0_cache import PortInterface
99 from soc.experiment.pimem import LDSTException
100 from soc.fu.regspec import RegSpecAPI
101
102 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
103 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
104 from openpower.decoder.power_decoder2 import Data
105 from openpower.consts import MSR
106 from soc.config.test.test_loadstore import TestMemPspec
107
108 # for debugging dcbz
109 from nmutil.util import Display
110
111
112 # TODO: LDSTInputData and LDSTOutputData really should be used
113 # here, to make things more like the other CompUnits. currently,
114 # also, RegSpecAPI is used explicitly here
115
116
117 class LDSTCompUnitRecord(CompUnitRecord):
118 def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
119 CompUnitRecord.__init__(self, opsubset, rwid,
120 n_src=3, n_dst=2, name=name)
121
122 self.ad = go_record(1, name="cu_ad") # address go in, req out
123 self.st = go_record(1, name="cu_st") # store go in, req out
124
125 self.exc_o = LDSTException("exc_o")
126
127 self.ld_o = Signal(reset_less=True) # operation is a LD
128 self.st_o = Signal(reset_less=True) # operation is a ST
129
130 # hmm... are these necessary?
131 self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
132 self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
133
134
135 class LDSTCompUnit(RegSpecAPI, Elaboratable):
136 """LOAD / STORE Computation Unit
137
138 Inputs
139 ------
140
141 * :pi: a PortInterface to the memory subsystem (read-write capable)
142 * :rwid: register width
143 * :awid: address width
144
145 Data inputs
146 -----------
147 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
148
149 Data (outputs)
150 --------------
151 * :o_data: Dest out (LD) - managed by wr[0] go/req
152 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
153 * :exc_o: Address/Data Exception occurred. LD/ST must terminate
154
155 TODO: make exc_o a data-type rather than a single-bit signal
156 (see bug #302)
157
158 Control Signals (In)
159 --------------------
160
161 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
162 * :issue_i: LD/ST is being "issued".
163 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
164 * :go_rd_i: read is being actioned (latches in src regs)
165 * :go_wr_i: write mode (exactly like ALU CompUnit)
166 * :go_ad_i: address is being actioned (triggers actual mem LD)
167 * :go_st_i: store is being actioned (triggers actual mem STORE)
168 * :go_die_i: resets the unit back to "wait for issue"
169
170 Control Signals (Out)
171 ---------------------
172
173 * :busy_o: function unit is busy
174 * :rd_rel_o: request src1/src2
175 * :adr_rel_o: request address (from mem)
176 * :sto_rel_o: request store (to mem)
177 * :req_rel_o: request write (result)
178 * :load_mem_o: activate memory LOAD
179 * :stwd_mem_o: activate memory STORE
180
181 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
182 in a single cycle and the CompUnit set back to doing another op.
183 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
184 depending on whether the operation is a ST or LD.
185
186 Note: LDSTCompUnit takes care of LE/BE normalisation:
187 * LD data is normalised after receipt from the PortInterface
188 * ST data is normalised *prior* to sending onto the PortInterface
189 TODO: use one module for the byte-reverse as it's quite expensive in gates
190 """
191
192 def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
193 debugtest=False, name=None):
194 super().__init__(rwid)
195 self.awid = awid
196 self.pi = pi
197 self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
198 self.debugtest = debugtest
199
200 # POWER-compliant LD/ST has index and update: *fixed* number of ports
201 self.n_src = n_src = 3 # RA, RB, RT/RS
202 self.n_dst = n_dst = 2 # RA, RT/RS
203
204 # set up array of src and dest signals
205 for i in range(n_src):
206 j = i + 1 # name numbering to match src1/src2
207 name = "src%d_i" % j
208 setattr(self, name, getattr(cu, name))
209
210 dst = []
211 for i in range(n_dst):
212 j = i + 1 # name numbering to match dest1/2...
213 name = "dest%d_o" % j
214 setattr(self, name, getattr(cu, name))
215
216 # convenience names
217 self.rd = cu.rd
218 self.wr = cu.wr
219 self.rdmaskn = cu.rdmaskn
220 self.wrmask = cu.wrmask
221 self.ad = cu.ad
222 self.st = cu.st
223 self.dest = cu._dest
224
225 # HACK: get data width from dest[0]. this is used across the board
226 # (it really shouldn't be)
227 self.data_wid = self.dest[0].shape()
228
229 self.go_rd_i = self.rd.go_i # temporary naming
230 self.go_wr_i = self.wr.go_i # temporary naming
231 self.go_ad_i = self.ad.go_i # temp naming: go address in
232 self.go_st_i = self.st.go_i # temp naming: go store in
233
234 self.rd_rel_o = self.rd.rel_o # temporary naming
235 self.req_rel_o = self.wr.rel_o # temporary naming
236 self.adr_rel_o = self.ad.rel_o # request address (from mem)
237 self.sto_rel_o = self.st.rel_o # request store (to mem)
238
239 self.issue_i = cu.issue_i
240 self.shadown_i = cu.shadown_i
241 self.go_die_i = cu.go_die_i
242
243 self.oper_i = cu.oper_i
244 self.src_i = cu._src_i
245
246 self.o_data = Data(self.data_wid, name="o") # Dest1 out: RT
247 self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
248 self.exc_o = cu.exc_o
249 self.done_o = cu.done_o
250 self.busy_o = cu.busy_o
251
252 self.ld_o = cu.ld_o
253 self.st_o = cu.st_o
254
255 self.load_mem_o = cu.load_mem_o
256 self.stwd_mem_o = cu.stwd_mem_o
257
258 def elaborate(self, platform):
259 m = Module()
260
261 # temp/convenience
262 comb = m.d.comb
263 sync = m.d.sync
264 issue_i = self.issue_i
265
266 #####################
267 # latches for the FSM.
268 m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
269 m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
270 m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
271 m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
272 m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
273 m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
274 m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
275 m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
276 m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
277 m.submodules.lsd_l = lsd_l = SRLatch(sync=False, name="lsd") # done
278
279 ####################
280 # signals
281
282 # opcode decode
283 op_is_ld = Signal(reset_less=True)
284 op_is_st = Signal(reset_less=True)
285 op_is_dcbz = Signal(reset_less=True)
286
287 # ALU/LD data output control
288 alu_valid = Signal(reset_less=True) # ALU operands are valid
289 alu_ok = Signal(reset_less=True) # ALU out ok (1 clock delay valid)
290 addr_ok = Signal(reset_less=True) # addr ok (from PortInterface)
291 ld_ok = Signal(reset_less=True) # LD out ok from PortInterface
292 wr_any = Signal(reset_less=True) # any write (incl. store)
293 rda_any = Signal(reset_less=True) # any read for address ops
294 rd_done = Signal(reset_less=True) # all *necessary* operands read
295 wr_reset = Signal(reset_less=True) # final reset condition
296
297 # LD and ALU out
298 alu_o = Signal(self.data_wid, reset_less=True)
299 ldd_o = Signal(self.data_wid, reset_less=True)
300
301 ##############################
302 # reset conditions for latches
303
304 # temporaries (also convenient when debugging)
305 reset_o = Signal(reset_less=True) # reset opcode
306 reset_w = Signal(reset_less=True) # reset write
307 reset_u = Signal(reset_less=True) # reset update
308 reset_a = Signal(reset_less=True) # reset adr latch
309 reset_i = Signal(reset_less=True) # issue|die (use a lot)
310 reset_r = Signal(self.n_src, reset_less=True) # reset src
311 reset_s = Signal(reset_less=True) # reset store
312
313 # end execution when a terminating condition is detected:
314 # - go_die_i: a speculative operation was cancelled
315 # - exc_o.happened: an exception has occurred
316 terminate = Signal()
317 comb += terminate.eq(self.go_die_i | self.exc_o.happened)
318
319 comb += reset_i.eq(issue_i | terminate) # various
320 comb += reset_o.eq(self.done_o | terminate) # opcode reset
321 comb += reset_w.eq(self.wr.go_i[0] | terminate) # write reg 1
322 comb += reset_u.eq(self.wr.go_i[1] | terminate) # update (reg 2)
323 comb += reset_s.eq(self.go_st_i | terminate) # store reset
324 comb += reset_r.eq(self.rd.go_i | Repl(terminate, self.n_src))
325 comb += reset_a.eq(self.go_ad_i | terminate)
326
327 p_st_go = Signal(reset_less=True)
328 sync += p_st_go.eq(self.st.go_i)
329
330 # decode bits of operand (latched)
331 oper_r = CompLDSTOpSubset(name="oper_r") # Dest register
332 comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE) # ST
333 comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD) # LD
334 comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ) # DCBZ
335 #uncomment if needed
336 #comb += Display("compldst_multi: op_is_dcbz = %i",
337 # (oper_r.insn_type == MicrOp.OP_DCBZ))
338 op_is_update = oper_r.ldst_mode == LDSTMode.update # UPDATE
339 op_is_cix = oper_r.ldst_mode == LDSTMode.cix # cache-inhibit
340 comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
341 comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
342 comb += self.ld_o.eq(op_is_ld)
343 comb += self.st_o.eq(op_is_st)
344
345 ##########################
346 # FSM implemented through sequence of latches. approximately this:
347 # - opc_l : opcode
348 # - src_l[0] : operands
349 # - src_l[1]
350 # - alu_l : looks after add of src1/2/imm (EA)
351 # - adr_l : waits for add (EA)
352 # - upd_l : waits for adr and Regfile (port 2)
353 # - src_l[2] : ST
354 # - lod_l : waits for adr (EA) and for LD Data
355 # - wri_l : waits for LD Data and Regfile (port 1)
356 # - st_l : waits for alu and operand2
357 # - rst_l : waits for all FSM paths to converge.
358 # NOTE: use sync to stop combinatorial loops.
359
360 # opcode latch - inverted so that busy resets to 0
361 # note this MUST be sync so as to avoid a combinatorial loop
362 # between busy_o and issue_i on the reset latch (rst_l)
363 sync += opc_l.s.eq(issue_i) # XXX NOTE: INVERTED FROM book!
364 sync += opc_l.r.eq(reset_o) # XXX NOTE: INVERTED FROM book!
365
366 # src operand latch
367 sync += src_l.s.eq(Repl(issue_i, self.n_src))
368 sync += src_l.r.eq(reset_r)
369
370 # alu latch. use sync-delay between alu_ok and valid to generate pulse
371 comb += alu_l.s.eq(reset_i)
372 comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
373
374 # addr latch
375 comb += adr_l.s.eq(reset_i)
376 sync += adr_l.r.eq(reset_a)
377
378 # ld latch
379 comb += lod_l.s.eq(reset_i)
380 comb += lod_l.r.eq(ld_ok)
381
382 # dest operand latch
383 comb += wri_l.s.eq(issue_i)
384 sync += wri_l.r.eq(reset_w | Repl(wr_reset |
385 (~self.pi.busy_o & op_is_update),
386 #(self.pi.busy_o & op_is_update),
387 #self.done_o | (self.pi.busy_o & op_is_update),
388 self.n_dst))
389
390 # update-mode operand latch (EA written to reg 2)
391 sync += upd_l.s.eq(reset_i)
392 sync += upd_l.r.eq(reset_u)
393
394 # store latch
395 comb += sto_l.s.eq(addr_ok & op_is_st)
396 sync += sto_l.r.eq(reset_s | p_st_go)
397
398 # ld/st done. needed to stop LD/ST from activating repeatedly
399 comb += lsd_l.s.eq(issue_i)
400 sync += lsd_l.r.eq(reset_s | p_st_go | ld_ok)
401
402 # reset latch
403 comb += rst_l.s.eq(addr_ok) # start when address is ready
404 comb += rst_l.r.eq(issue_i)
405
406 # create a latch/register for the operand
407 with m.If(self.issue_i):
408 sync += oper_r.eq(self.oper_i)
409 with m.If(self.done_o | terminate):
410 sync += oper_r.eq(0)
411
412 # and for LD
413 ldd_r = Signal(self.data_wid, reset_less=True) # Dest register
414 latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
415
416 # and for each input from the incoming src operands
417 srl = []
418 for i in range(self.n_src):
419 name = "src_r%d" % i
420 src_r = Signal(self.data_wid, name=name, reset_less=True)
421 with m.If(self.rd.go_i[i]):
422 sync += src_r.eq(self.src_i[i])
423 with m.If(self.issue_i):
424 sync += src_r.eq(0)
425 srl.append(src_r)
426
427 # and one for the output from the ADD (for the EA)
428 addr_r = Signal(self.data_wid, reset_less=True) # Effective Address
429 latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
430
431 # select either zero or src1 if opcode says so
432 op_is_z = oper_r.zero_a
433 src1_or_z = Signal(self.data_wid, reset_less=True)
434 m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
435
436 # select either immediate or src2 if opcode says so
437 op_is_imm = oper_r.imm_data.ok
438 src2_or_imm = Signal(self.data_wid, reset_less=True)
439 m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.data, srl[1]))
440
441 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
442 comb += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
443 m.d.sync += alu_ok.eq(alu_valid) # keep ack in sync with EA
444
445 ############################
446 # Control Signal calculation
447
448 # busy signal
449 busy_o = self.busy_o
450 comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o) # busy out
451
452 # 1st operand read-request only when zero not active
453 # 2nd operand only needed when immediate is not active
454 slg = Cat(op_is_z, op_is_imm)
455 bro = Repl(self.busy_o, self.n_src)
456 comb += self.rd.rel_o.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
457
458 # note when the address-related read "go" signals are active
459 comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
460
461 # alu input valid when 1st and 2nd ops done (or imm not active)
462 comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]))
463
464 # 3rd operand only needed when operation is a store
465 comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
466
467 # all reads done when alu is valid and 3rd operand needed
468 comb += rd_done.eq(alu_valid & ~self.rd.rel_o[2])
469
470 # address release only if addr ready, but Port must be idle
471 comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
472
473 # the write/store (etc) all must be cancelled if an exception occurs
474 # note: cancel is active low, like shadown_i,
475 # while exc_o.happpened is active high
476 cancel = Signal(reset_less=True)
477 comb += cancel.eq(~self.exc_o.happened & self.shadown_i)
478
479 # store release when st ready *and* all operands read (and no shadow)
480 comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st &
481 cancel)
482
483 # request write of LD result. waits until shadow is dropped.
484 comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
485 op_is_ld & cancel)
486
487 # request write of EA result only in update mode
488 comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
489 alu_valid & cancel)
490
491 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
492 comb += wr_any.eq(self.st.go_i | p_st_go |
493 self.wr.go_i[0] | self.wr.go_i[1])
494 comb += wr_reset.eq(rst_l.q & busy_o & cancel &
495 ~(self.st.rel_o | self.wr.rel_o[0] |
496 self.wr.rel_o[1]) &
497 (lod_l.qn | op_is_st)
498 )
499 comb += self.done_o.eq(wr_reset & (~self.pi.busy_o | op_is_ld))
500
501 ######################
502 # Data/Address outputs
503
504 # put the LD-output register directly onto the output bus on a go_write
505 comb += self.o_data.data.eq(self.dest[0])
506 with m.If(self.wr.go_i[0]):
507 comb += self.dest[0].eq(ldd_r)
508
509 # "update" mode, put address out on 2nd go-write
510 comb += self.addr_o.data.eq(self.dest[1])
511 with m.If(op_is_update & self.wr.go_i[1]):
512 comb += self.dest[1].eq(addr_r)
513
514 # need to look like MultiCompUnit: put wrmask out.
515 # XXX may need to make this enable only when write active
516 comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
517
518 ###########################
519 # PortInterface connections
520 pi = self.pi
521
522 # connect to LD/ST PortInterface.
523 comb += pi.is_ld_i.eq(op_is_ld & busy_o) # decoded-LD
524 comb += pi.is_st_i.eq(op_is_st & busy_o) # decoded-ST
525 comb += pi.is_dcbz_i.eq(op_is_dcbz & busy_o) # decoded-DCBZ
526 comb += pi.data_len.eq(oper_r.data_len) # data_len
527 # address: use sync to avoid long latency
528 sync += pi.addr.data.eq(addr_r) # EA from adder
529 sync += Display("EA from adder %i op_is_dcbz %i",addr_r,op_is_dcbz)
530 ## do not use ### sync += pi.is_dcbz.eq(op_is_dcbz) # set dcbz
531
532 sync += pi.addr.ok.eq(alu_ok & lsd_l.q) # "do address stuff" (once)
533 comb += self.exc_o.eq(pi.exc_o) # exception occurred
534 comb += addr_ok.eq(self.pi.addr_ok_o) # no exc, address fine
535 # connect MSR.PR for priv/virt operation
536 comb += pi.msr_pr.eq(oper_r.msr[MSR.PR])
537
538 # byte-reverse on LD
539 revnorev = Signal(64, reset_less=True)
540 with m.If(oper_r.byte_reverse):
541 # byte-reverse the data based on ld/st width (turn it to LE)
542 data_len = oper_r.data_len
543 lddata_r = byte_reverse(m, 'lddata_r', pi.ld.data, data_len)
544 comb += revnorev.eq(lddata_r) # put reversed- data out
545 with m.Else():
546 comb += revnorev.eq(pi.ld.data) # put data out, straight (as BE)
547
548 # then check sign-extend
549 with m.If(oper_r.sign_extend):
550 # okok really should "if data_len == 4" and so on here
551 with m.If(oper_r.data_len == 2):
552 comb += ldd_o.eq(exts(revnorev, 16, 64)) # sign-extend hword
553 with m.Else():
554 comb += ldd_o.eq(exts(revnorev, 32, 64)) # sign-extend dword
555 with m.Else():
556 comb += ldd_o.eq(revnorev)
557
558 # ld - ld gets latched in via lod_l
559 comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
560
561 # byte-reverse on ST
562 op3 = srl[2] # 3rd operand latch
563 with m.If(oper_r.byte_reverse):
564 # byte-reverse the data based on width
565 data_len = oper_r.data_len
566 stdata_r = byte_reverse(m, 'stdata_r', op3, data_len)
567 comb += pi.st.data.eq(stdata_r)
568 with m.Else():
569 comb += pi.st.data.eq(op3)
570 # store - data goes in based on go_st
571 comb += pi.st.ok.eq(self.st.go_i) # go store signals st data valid
572
573 return m
574
575 def get_out(self, i):
576 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
577 to LDSTOutputData o and o1 respectively.
578 """
579 if i == 0:
580 return self.o_data # LDSTOutputData.regspec o
581 if i == 1:
582 return self.addr_o # LDSTOutputData.regspec o1
583 # return self.dest[i]
584
585 def get_fu_out(self, i):
586 return self.get_out(i)
587
588 def __iter__(self):
589 yield self.rd.go_i
590 yield self.go_ad_i
591 yield self.wr.go_i
592 yield self.go_st_i
593 yield self.issue_i
594 yield self.shadown_i
595 yield self.go_die_i
596 yield from self.oper_i.ports()
597 yield from self.src_i
598 yield self.busy_o
599 yield self.rd.rel_o
600 yield self.adr_rel_o
601 yield self.sto_rel_o
602 yield self.wr.rel_o
603 yield from self.o_data.ports()
604 yield from self.addr_o.ports()
605 yield self.load_mem_o
606 yield self.stwd_mem_o
607
608 def ports(self):
609 return list(self)
610
611
612 def wait_for(sig, wait=True, test1st=False):
613 v = (yield sig)
614 print("wait for", sig, v, wait, test1st)
615 if test1st and bool(v) == wait:
616 return
617 while True:
618 yield
619 v = (yield sig)
620 #print("...wait for", sig, v)
621 if bool(v) == wait:
622 break
623
624
625 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
626 byterev=True):
627 print("ST", src1, src2, src3, imm, imm_ok, update)
628 yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)
629 yield dut.oper_i.data_len.eq(2) # half-word
630 yield dut.oper_i.byte_reverse.eq(byterev)
631 yield dut.src1_i.eq(src1)
632 yield dut.src2_i.eq(src2)
633 yield dut.src3_i.eq(src3)
634 yield dut.oper_i.imm_data.data.eq(imm)
635 yield dut.oper_i.imm_data.ok.eq(imm_ok)
636 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
637 yield dut.issue_i.eq(1)
638 yield
639 yield dut.issue_i.eq(0)
640
641 if imm_ok:
642 active_rel = 0b101
643 else:
644 active_rel = 0b111
645 # wait for all active rel signals to come up
646 while True:
647 rel = yield dut.rd.rel_o
648 if rel == active_rel:
649 break
650 yield
651 yield dut.rd.go_i.eq(active_rel)
652 yield
653 yield dut.rd.go_i.eq(0)
654
655 yield from wait_for(dut.adr_rel_o, False, test1st=True)
656 # yield from wait_for(dut.adr_rel_o)
657 # yield dut.ad.go.eq(1)
658 # yield
659 # yield dut.ad.go.eq(0)
660
661 if update:
662 yield from wait_for(dut.wr.rel_o[1])
663 yield dut.wr.go.eq(0b10)
664 yield
665 addr = yield dut.addr_o
666 print("addr", addr)
667 yield dut.wr.go.eq(0)
668 else:
669 addr = None
670
671 yield from wait_for(dut.sto_rel_o)
672 yield dut.go_st_i.eq(1)
673 yield
674 yield dut.go_st_i.eq(0)
675 yield from wait_for(dut.busy_o, False)
676 # wait_for(dut.stwd_mem_o)
677 yield
678 return addr
679
680
681 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
682 byterev=True):
683 print("LD", src1, src2, imm, imm_ok, update)
684 yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
685 yield dut.oper_i.data_len.eq(2) # half-word
686 yield dut.oper_i.byte_reverse.eq(byterev)
687 yield dut.src1_i.eq(src1)
688 yield dut.src2_i.eq(src2)
689 yield dut.oper_i.zero_a.eq(zero_a)
690 yield dut.oper_i.imm_data.data.eq(imm)
691 yield dut.oper_i.imm_data.ok.eq(imm_ok)
692 yield dut.issue_i.eq(1)
693 yield
694 yield dut.issue_i.eq(0)
695 yield
696
697 # set up read-operand flags
698 rd = 0b00
699 if not imm_ok: # no immediate means RB register needs to be read
700 rd |= 0b10
701 if not zero_a: # no zero-a means RA needs to be read
702 rd |= 0b01
703
704 # wait for the operands (RA, RB, or both)
705 if rd:
706 yield dut.rd.go_i.eq(rd)
707 yield from wait_for(dut.rd.rel_o)
708 yield dut.rd.go_i.eq(0)
709
710 yield from wait_for(dut.adr_rel_o, False, test1st=True)
711 # yield dut.ad.go.eq(1)
712 # yield
713 # yield dut.ad.go.eq(0)
714
715 if update:
716 yield from wait_for(dut.wr.rel_o[1])
717 yield dut.wr.go.eq(0b10)
718 yield
719 addr = yield dut.addr_o
720 print("addr", addr)
721 yield dut.wr.go.eq(0)
722 else:
723 addr = None
724
725 yield from wait_for(dut.wr.rel_o[0], test1st=True)
726 yield dut.wr.go.eq(1)
727 yield
728 data = yield dut.o_data
729 print(data)
730 yield dut.wr.go.eq(0)
731 yield from wait_for(dut.busy_o)
732 yield
733 # wait_for(dut.stwd_mem_o)
734 return data, addr
735
736
737 def ldst_sim(dut):
738
739 ###################
740 # immediate version
741
742 # two STs (different addresses)
743 yield from store(dut, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
744 yield from store(dut, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
745 yield
746 # two LDs (deliberately LD from the 1st address then 2nd)
747 data, addr = yield from load(dut, 4, 0, 2)
748 assert data == 0x0003, "returned %x" % data
749 data, addr = yield from load(dut, 2, 0, 2)
750 assert data == 0x0009, "returned %x" % data
751 yield
752
753 # indexed version
754 yield from store(dut, 9, 5, 3, 0, imm_ok=False)
755 data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
756 assert data == 0x0003, "returned %x" % data
757
758 # update-immediate version
759 addr = yield from store(dut, 9, 6, 3, 2, update=True)
760 assert addr == 0x000b, "returned %x" % addr
761
762 # update-indexed version
763 data, addr = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
764 assert data == 0x0003, "returned %x" % data
765 assert addr == 0x000e, "returned %x" % addr
766
767 # immediate *and* zero version
768 data, addr = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
769 assert data == 0x0008, "returned %x" % data
770
771
772 class TestLDSTCompUnit(LDSTCompUnit):
773
774 def __init__(self, rwid, pspec):
775 from soc.experiment.l0_cache import TstL0CacheBuffer
776 self.l0 = l0 = TstL0CacheBuffer(pspec)
777 pi = l0.l0.dports[0]
778 LDSTCompUnit.__init__(self, pi, rwid, 4)
779
780 def elaborate(self, platform):
781 m = LDSTCompUnit.elaborate(self, platform)
782 m.submodules.l0 = self.l0
783 # link addr-go direct to rel
784 m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
785 return m
786
787
788 def test_scoreboard():
789
790 units = {}
791 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
792 imem_ifacetype='bare_wb',
793 addr_wid=48,
794 mask_wid=8,
795 reg_wid=64,
796 units=units)
797
798 dut = TestLDSTCompUnit(16,pspec)
799 vl = rtlil.convert(dut, ports=dut.ports())
800 with open("test_ldst_comp.il", "w") as f:
801 f.write(vl)
802
803 run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
804
805
806 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
807
808 def __init__(self, pspec):
809 from soc.experiment.l0_cache import TstL0CacheBuffer
810 from soc.fu.ldst.pipe_data import LDSTPipeSpec
811 regspec = LDSTPipeSpec.regspec
812 self.l0 = l0 = TstL0CacheBuffer(pspec)
813 pi = l0.l0.dports[0]
814 LDSTCompUnit.__init__(self, pi, regspec, 4)
815
816 def elaborate(self, platform):
817 m = LDSTCompUnit.elaborate(self, platform)
818 m.submodules.l0 = self.l0
819 # link addr-go direct to rel
820 m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
821 return m
822
823
824 def test_scoreboard_regspec():
825
826 units = {}
827 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
828 imem_ifacetype='bare_wb',
829 addr_wid=48,
830 mask_wid=8,
831 reg_wid=64,
832 units=units)
833
834 dut = TestLDSTCompUnitRegSpec(pspec)
835 vl = rtlil.convert(dut, ports=dut.ports())
836 with open("test_ldst_comp.il", "w") as f:
837 f.write(vl)
838
839 run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
840
841
842 if __name__ == '__main__':
843 test_scoreboard_regspec()
844 test_scoreboard()