1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
87 from nmutil
.byterev
import byte_reverse
88 from nmutil
.extend
import exts
90 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
91 from soc
.experiment
.l0_cache
import PortInterface
92 from soc
.fu
.regspec
import RegSpecAPI
94 from soc
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
95 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
96 from soc
.decoder
.power_decoder2
import Data
99 class LDSTCompUnitRecord(CompUnitRecord
):
100 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
101 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
102 n_src
=3, n_dst
=2, name
=name
)
104 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
105 self
.st
= go_record(1, name
="cu_st") # store go in, req out
107 self
.addr_exc_o
= Signal(reset_less
=True) # address exception
109 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
110 self
.st_o
= Signal(reset_less
=True) # operation is a ST
112 # hmm... are these necessary?
113 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
114 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
117 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
118 """LOAD / STORE Computation Unit
123 * :pi: a PortInterface to the memory subsystem (read-write capable)
124 * :rwid: register width
125 * :awid: address width
129 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
133 * :data_o: Dest out (LD) - managed by wr[0] go/req
134 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
135 * :addr_exc_o: Address/Data Exception occurred. LD/ST must terminate
137 TODO: make addr_exc_o a data-type rather than a single-bit signal
143 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
144 * :issue_i: LD/ST is being "issued".
145 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
146 * :go_rd_i: read is being actioned (latches in src regs)
147 * :go_wr_i: write mode (exactly like ALU CompUnit)
148 * :go_ad_i: address is being actioned (triggers actual mem LD)
149 * :go_st_i: store is being actioned (triggers actual mem STORE)
150 * :go_die_i: resets the unit back to "wait for issue"
152 Control Signals (Out)
153 ---------------------
155 * :busy_o: function unit is busy
156 * :rd_rel_o: request src1/src2
157 * :adr_rel_o: request address (from mem)
158 * :sto_rel_o: request store (to mem)
159 * :req_rel_o: request write (result)
160 * :load_mem_o: activate memory LOAD
161 * :stwd_mem_o: activate memory STORE
163 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
164 in a single cycle and the CompUnit set back to doing another op.
165 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
166 depending on whether the operation is a ST or LD.
168 Note: LDSTCompUnit takes care of LE/BE normalisation:
169 * LD data is normalised after receipt from the PortInterface
170 * ST data is normalised *prior* to sending onto the PortInterface
171 TODO: use one module for the byte-reverse as it's quite expensive in gates
174 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
175 debugtest
=False, name
=None):
176 super().__init
__(rwid
)
179 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
180 self
.debugtest
= debugtest
182 # POWER-compliant LD/ST has index and update: *fixed* number of ports
183 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
184 self
.n_dst
= n_dst
= 2 # RA, RT/RS
186 # set up array of src and dest signals
187 for i
in range(n_src
):
188 j
= i
+ 1 # name numbering to match src1/src2
190 setattr(self
, name
, getattr(cu
, name
))
193 for i
in range(n_dst
):
194 j
= i
+ 1 # name numbering to match dest1/2...
195 name
= "dest%d_o" % j
196 setattr(self
, name
, getattr(cu
, name
))
201 self
.rdmaskn
= cu
.rdmaskn
202 self
.wrmask
= cu
.wrmask
207 # HACK: get data width from dest[0]. this is used across the board
208 # (it really shouldn't be)
209 self
.data_wid
= self
.dest
[0].shape()
211 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
212 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
213 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
214 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
216 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
217 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
218 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
219 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
221 self
.issue_i
= cu
.issue_i
222 self
.shadown_i
= cu
.shadown_i
223 self
.go_die_i
= cu
.go_die_i
225 self
.oper_i
= cu
.oper_i
226 self
.src_i
= cu
._src
_i
228 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
229 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
230 self
.addr_exc_o
= cu
.addr_exc_o
231 self
.done_o
= cu
.done_o
232 self
.busy_o
= cu
.busy_o
237 self
.load_mem_o
= cu
.load_mem_o
238 self
.stwd_mem_o
= cu
.stwd_mem_o
240 def elaborate(self
, platform
):
246 issue_i
= self
.issue_i
248 #####################
249 # latches for the FSM.
250 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
251 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
252 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
253 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
254 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
255 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
256 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
257 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
258 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
259 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
265 op_is_ld
= Signal(reset_less
=True)
266 op_is_st
= Signal(reset_less
=True)
268 # ALU/LD data output control
269 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
270 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
271 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
272 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
273 wr_any
= Signal(reset_less
=True) # any write (incl. store)
274 rda_any
= Signal(reset_less
=True) # any read for address ops
275 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
276 wr_reset
= Signal(reset_less
=True) # final reset condition
279 alu_o
= Signal(self
.data_wid
, reset_less
=True)
280 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
282 ##############################
283 # reset conditions for latches
285 # temporaries (also convenient when debugging)
286 reset_o
= Signal(reset_less
=True) # reset opcode
287 reset_w
= Signal(reset_less
=True) # reset write
288 reset_u
= Signal(reset_less
=True) # reset update
289 reset_a
= Signal(reset_less
=True) # reset adr latch
290 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
291 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
292 reset_s
= Signal(reset_less
=True) # reset store
294 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
295 comb
+= reset_o
.eq(self
.done_o | self
.go_die_i
) # opcode reset
296 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | self
.go_die_i
) # write reg 1
297 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | self
.go_die_i
) # update (reg 2)
298 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
299 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(self
.go_die_i
, self
.n_src
))
300 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
302 p_st_go
= Signal(reset_less
=True)
303 sync
+= p_st_go
.eq(self
.st
.go_i
)
305 # decode bits of operand (latched)
306 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
307 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
308 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
309 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
310 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
311 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
312 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
313 comb
+= self
.ld_o
.eq(op_is_ld
)
314 comb
+= self
.st_o
.eq(op_is_st
)
316 ##########################
317 # FSM implemented through sequence of latches. approximately this:
319 # - src_l[0] : operands
321 # - alu_l : looks after add of src1/2/imm (EA)
322 # - adr_l : waits for add (EA)
323 # - upd_l : waits for adr and Regfile (port 2)
325 # - lod_l : waits for adr (EA) and for LD Data
326 # - wri_l : waits for LD Data and Regfile (port 1)
327 # - st_l : waits for alu and operand2
328 # - rst_l : waits for all FSM paths to converge.
329 # NOTE: use sync to stop combinatorial loops.
331 # opcode latch - inverted so that busy resets to 0
332 # note this MUST be sync so as to avoid a combinatorial loop
333 # between busy_o and issue_i on the reset latch (rst_l)
334 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
335 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
338 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
339 sync
+= src_l
.r
.eq(reset_r
)
341 # alu latch. use sync-delay between alu_ok and valid to generate pulse
342 comb
+= alu_l
.s
.eq(reset_i
)
343 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
346 comb
+= adr_l
.s
.eq(reset_i
)
347 sync
+= adr_l
.r
.eq(reset_a
)
350 comb
+= lod_l
.s
.eq(reset_i
)
351 comb
+= lod_l
.r
.eq(ld_ok
)
354 comb
+= wri_l
.s
.eq(issue_i
)
355 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
356 (~self
.pi
.busy_o
& op_is_update
),
357 #(self.pi.busy_o & op_is_update),
358 #self.done_o | (self.pi.busy_o & op_is_update),
361 # update-mode operand latch (EA written to reg 2)
362 sync
+= upd_l
.s
.eq(reset_i
)
363 sync
+= upd_l
.r
.eq(reset_u
)
366 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
367 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
369 # ld/st done. needed to stop LD/ST from activating repeatedly
370 comb
+= lsd_l
.s
.eq(issue_i
)
371 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
374 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
375 comb
+= rst_l
.r
.eq(issue_i
)
377 # create a latch/register for the operand
378 with m
.If(self
.issue_i
):
379 sync
+= oper_r
.eq(self
.oper_i
)
380 with m
.If(self
.done_o
):
384 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
385 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
387 # and for each input from the incoming src operands
389 for i
in range(self
.n_src
):
391 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
392 with m
.If(self
.rd
.go_i
[i
]):
393 sync
+= src_r
.eq(self
.src_i
[i
])
394 with m
.If(self
.issue_i
):
398 # and one for the output from the ADD (for the EA)
399 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
400 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
402 # select either zero or src1 if opcode says so
403 op_is_z
= oper_r
.zero_a
404 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
405 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
407 # select either immediate or src2 if opcode says so
408 op_is_imm
= oper_r
.imm_data
.ok
409 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
410 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
412 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
413 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
414 m
.d
.sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
416 ############################
417 # Control Signal calculation
421 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
423 # 1st operand read-request only when zero not active
424 # 2nd operand only needed when immediate is not active
425 slg
= Cat(op_is_z
, op_is_imm
)
426 bro
= Repl(self
.busy_o
, self
.n_src
)
427 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
429 # note when the address-related read "go" signals are active
430 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
432 # alu input valid when 1st and 2nd ops done (or imm not active)
433 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]))
435 # 3rd operand only needed when operation is a store
436 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
438 # all reads done when alu is valid and 3rd operand needed
439 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
441 # address release only if addr ready, but Port must be idle
442 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
444 # store release when st ready *and* all operands read (and no shadow)
445 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
448 # request write of LD result. waits until shadow is dropped.
449 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
450 op_is_ld
& self
.shadown_i
)
452 # request write of EA result only in update mode
453 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
454 alu_valid
& self
.shadown_i
)
456 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
457 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
458 self
.wr
.go_i
[0] | self
.wr
.go_i
[1])
459 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
&
460 ~
(self
.st
.rel_o | self
.wr
.rel_o
[0] |
462 (lod_l
.qn | op_is_st
)
464 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
466 ######################
467 # Data/Address outputs
469 # put the LD-output register directly onto the output bus on a go_write
470 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
471 with m
.If(self
.wr
.go_i
[0]):
472 comb
+= self
.dest
[0].eq(ldd_r
)
474 # "update" mode, put address out on 2nd go-write
475 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
476 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
477 comb
+= self
.dest
[1].eq(addr_r
)
479 # need to look like MultiCompUnit: put wrmask out.
480 # XXX may need to make this enable only when write active
481 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
483 ###########################
484 # PortInterface connections
487 # connect to LD/ST PortInterface.
488 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
489 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
490 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
491 # address: use sync to avoid long latency
492 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
493 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
494 comb
+= self
.addr_exc_o
.eq(pi
.addr_exc_o
) # exception occurred
495 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
498 revnorev
= Signal(64, reset_less
=True)
499 with m
.If(oper_r
.byte_reverse
):
500 # byte-reverse the data based on ld/st width (turn it to LE)
501 data_len
= oper_r
.data_len
502 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
503 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
505 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
507 # then check sign-extend
508 with m
.If(oper_r
.sign_extend
):
509 # okok really should "if data_len == 4" and so on here
510 with m
.If(oper_r
.data_len
== 2):
511 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
513 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
515 comb
+= ldd_o
.eq(revnorev
)
517 # ld - ld gets latched in via lod_l
518 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
521 op3
= srl
[2] # 3rd operand latch
522 with m
.If(oper_r
.byte_reverse
):
523 # byte-reverse the data based on width
524 data_len
= oper_r
.data_len
525 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
526 comb
+= pi
.st
.data
.eq(stdata_r
)
528 comb
+= pi
.st
.data
.eq(op3
)
529 # store - data goes in based on go_st
530 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
534 def get_out(self
, i
):
535 """make LDSTCompUnit look like RegSpecALUAPI"""
540 # return self.dest[i]
542 def get_fu_out(self
, i
):
543 return self
.get_out(i
)
553 yield from self
.oper_i
.ports()
554 yield from self
.src_i
560 yield from self
.data_o
.ports()
561 yield from self
.addr_o
.ports()
562 yield self
.load_mem_o
563 yield self
.stwd_mem_o
569 def wait_for(sig
, wait
=True, test1st
=False):
571 print("wait for", sig
, v
, wait
, test1st
)
572 if test1st
and bool(v
) == wait
:
577 #print("...wait for", sig, v)
582 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
584 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
585 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
586 yield dut
.oper_i
.data_len
.eq(2) # half-word
587 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
588 yield dut
.src1_i
.eq(src1
)
589 yield dut
.src2_i
.eq(src2
)
590 yield dut
.src3_i
.eq(src3
)
591 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
592 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
593 yield dut
.oper_i
.update
.eq(update
)
594 yield dut
.issue_i
.eq(1)
596 yield dut
.issue_i
.eq(0)
602 # wait for all active rel signals to come up
604 rel
= yield dut
.rd
.rel_o
605 if rel
== active_rel
:
608 yield dut
.rd
.go
.eq(active_rel
)
610 yield dut
.rd
.go
.eq(0)
612 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
613 # yield from wait_for(dut.adr_rel_o)
614 # yield dut.ad.go.eq(1)
616 # yield dut.ad.go.eq(0)
619 yield from wait_for(dut
.wr
.rel_o
[1])
620 yield dut
.wr
.go
.eq(0b10)
622 addr
= yield dut
.addr_o
624 yield dut
.wr
.go
.eq(0)
628 yield from wait_for(dut
.sto_rel_o
)
629 yield dut
.go_st_i
.eq(1)
631 yield dut
.go_st_i
.eq(0)
632 yield from wait_for(dut
.busy_o
, False)
633 # wait_for(dut.stwd_mem_o)
638 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
640 print("LD", src1
, src2
, imm
, imm_ok
, update
)
641 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
642 yield dut
.oper_i
.data_len
.eq(2) # half-word
643 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
644 yield dut
.src1_i
.eq(src1
)
645 yield dut
.src2_i
.eq(src2
)
646 yield dut
.oper_i
.zero_a
.eq(zero_a
)
647 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
648 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
649 yield dut
.issue_i
.eq(1)
651 yield dut
.issue_i
.eq(0)
654 # set up read-operand flags
656 if not imm_ok
: # no immediate means RB register needs to be read
658 if not zero_a
: # no zero-a means RA needs to be read
661 # wait for the operands (RA, RB, or both)
663 yield dut
.rd
.go
.eq(rd
)
664 yield from wait_for(dut
.rd
.rel_o
)
665 yield dut
.rd
.go
.eq(0)
667 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
668 # yield dut.ad.go.eq(1)
670 # yield dut.ad.go.eq(0)
673 yield from wait_for(dut
.wr
.rel_o
[1])
674 yield dut
.wr
.go
.eq(0b10)
676 addr
= yield dut
.addr_o
678 yield dut
.wr
.go
.eq(0)
682 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
683 yield dut
.wr
.go
.eq(1)
685 data
= yield dut
.data_o
687 yield dut
.wr
.go
.eq(0)
688 yield from wait_for(dut
.busy_o
)
690 # wait_for(dut.stwd_mem_o)
699 # two STs (different addresses)
700 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
701 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
703 # two LDs (deliberately LD from the 1st address then 2nd)
704 data
, addr
= yield from load(dut
, 4, 0, 2)
705 assert data
== 0x0003, "returned %x" % data
706 data
, addr
= yield from load(dut
, 2, 0, 2)
707 assert data
== 0x0009, "returned %x" % data
711 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
712 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
713 assert data
== 0x0003, "returned %x" % data
715 # update-immediate version
716 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
717 assert addr
== 0x000b, "returned %x" % addr
719 # update-indexed version
720 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
721 assert data
== 0x0003, "returned %x" % data
722 assert addr
== 0x000e, "returned %x" % addr
724 # immediate *and* zero version
725 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
726 assert data
== 0x0008, "returned %x" % data
729 class TestLDSTCompUnit(LDSTCompUnit
):
731 def __init__(self
, rwid
):
732 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
733 self
.l0
= l0
= TstL0CacheBuffer()
734 pi
= l0
.l0
.dports
[0].pi
735 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
737 def elaborate(self
, platform
):
738 m
= LDSTCompUnit
.elaborate(self
, platform
)
739 m
.submodules
.l0
= self
.l0
740 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
744 def test_scoreboard():
746 dut
= TestLDSTCompUnit(16)
747 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
748 with
open("test_ldst_comp.il", "w") as f
:
751 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
754 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
757 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
758 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
759 regspec
= LDSTPipeSpec
.regspec
760 self
.l0
= l0
= TstL0CacheBuffer()
761 pi
= l0
.l0
.dports
[0].pi
762 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
764 def elaborate(self
, platform
):
765 m
= LDSTCompUnit
.elaborate(self
, platform
)
766 m
.submodules
.l0
= self
.l0
767 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
771 def test_scoreboard_regspec():
773 dut
= TestLDSTCompUnitRegSpec()
774 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
775 with
open("test_ldst_comp.il", "w") as f
:
778 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
781 if __name__
== '__main__':
782 test_scoreboard_regspec()