src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 TODO: dcbz, yes, that's going to be complicated, has to be done
  24  with great care, to detect the case when dcbz is set
  25  and *not* expect to read any data, just the address.
  26  so, wait for RA but not RB.
  27
  28 Both LD and ST may request that the address be computed from summing
  29 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  30 the immediate (from the opcode).
  31
  32 Both LD and ST may also request "update" mode (op_is_update) which
  33 activates the use of Go_Write[1] to control storage of the EA into
  34 a *second* operand in the register file.
  35
  36 Thus this module has *TWO* write-requests to the register file and
  37 *THREE* read-requests to the register file (not all at the same time!)
  38 The regfile port usage is:
  39
  40     * LD-imm         1R1W
  41     * LD-imm-update  1R2W
  42     * LD-idx         2R1W
  43     * LD-idx-update  2R2W
  44
  45     * ST-imm         2R
  46     * ST-imm-update  2R1W
  47     * ST-idx         3R
  48     * ST-idx-update  3R1W
  49
  50 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  51 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  52 the nested FSMs below are *combinatorial*).
  53
  54     * One FSM covers Operand collection and communication address-side
  55       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  56
  57     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  58
  59     * A third FSM activates to cover ST.  it activates if op_is_st is true
  60
  61     * TODO document DCBZ (not complete yet)
  62
  63     * The "overall" (fourth) FSM coordinates the progression and completion
  64       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  65
  66 Full diagram:
  67
  68     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  69
  70 Links including to walk-through videos:
  71
  72     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  73     * http://libre-soc.org/openpower/isa/fixedload
  74     * http://libre-soc.org/openpower/isa/fixedstore
  75
  76 Related Bugreports:
  77
  78     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  79     * https://bugs.libre-soc.org/show_bug.cgi?id=216
  80
  81 Terminology:
  82
  83     * EA - Effective Address
  84     * LD - Load
  85     * ST - Store
  86 """
  87
  88 from nmigen.compat.sim import run_simulation
  89 from nmigen.cli import verilog, rtlil
  90 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl, C
  91 from nmigen.hdl.rec import Record, Layout
  92
  93 from nmutil.latch import SRLatch, latchregister
  94 from nmutil.byterev import byte_reverse
  95 from nmutil.extend import exts
  96
  97 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  98 from soc.experiment.l0_cache import PortInterface
  99 from soc.experiment.pimem import LDSTException
 100 from soc.fu.regspec import RegSpecAPI
 101
 102 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
 103 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
 104 from openpower.decoder.power_decoder2 import Data
 105 from openpower.consts import MSR
 106 from soc.config.test.test_loadstore import TestMemPspec
 107
 108 # for debugging dcbz
 109 from nmutil.util import Display
 110
 111
 112 # TODO: LDSTInputData and LDSTOutputData really should be used
 113 # here, to make things more like the other CompUnits.  currently,
 114 # also, RegSpecAPI is used explicitly here
 115
 116
 117 class LDSTCompUnitRecord(CompUnitRecord):
 118     def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
 119         CompUnitRecord.__init__(self, opsubset, rwid,
 120                                 n_src=3, n_dst=2, name=name)
 121
 122         self.ad = go_record(1, name="cu_ad")  # address go in, req out
 123         self.st = go_record(1, name="cu_st")  # store go in, req out
 124
 125         self.exc_o = LDSTException("exc_o")
 126
 127         self.ld_o = Signal(reset_less=True)  # operation is a LD
 128         self.st_o = Signal(reset_less=True)  # operation is a ST
 129
 130         # hmm... are these necessary?
 131         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 132         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 133
 134
 135 class LDSTCompUnit(RegSpecAPI, Elaboratable):
 136     """LOAD / STORE Computation Unit
 137
 138     Inputs
 139     ------
 140
 141     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 142     * :rwid:   register width
 143     * :awid:   address width
 144
 145     Data inputs
 146     -----------
 147     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 148
 149     Data (outputs)
 150     --------------
 151     * :o_data:  Dest out (LD)          - managed by wr[0] go/req
 152     * :addr_o:  Address out (LD or ST) - managed by wr[1] go/req
 153     * :exc_o:   Address/Data Exception occurred.  LD/ST must terminate
 154
 155     TODO: make exc_o a data-type rather than a single-bit signal
 156           (see bug #302)
 157
 158     Control Signals (In)
 159     --------------------
 160
 161     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 162     * :issue_i:    LD/ST is being "issued".
 163     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 164     * :go_rd_i:    read is being actioned (latches in src regs)
 165     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 166     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 167     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 168     * :go_die_i:   resets the unit back to "wait for issue"
 169
 170     Control Signals (Out)
 171     ---------------------
 172
 173     * :busy_o:      function unit is busy
 174     * :rd_rel_o:    request src1/src2
 175     * :adr_rel_o:   request address (from mem)
 176     * :sto_rel_o:   request store (to mem)
 177     * :req_rel_o:   request write (result)
 178     * :load_mem_o:  activate memory LOAD
 179     * :stwd_mem_o:  activate memory STORE
 180
 181     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 182     in a single cycle and the CompUnit set back to doing another op.
 183     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 184     depending on whether the operation is a ST or LD.
 185
 186     Note: LDSTCompUnit takes care of LE/BE normalisation:
 187     * LD data is normalised after receipt from the PortInterface
 188     * ST data is normalised *prior* to sending onto the PortInterface
 189     TODO: use one module for the byte-reverse as it's quite expensive in gates
 190     """
 191
 192     def __init__(self, pi=None, rwid=64, awid=64, opsubset=CompLDSTOpSubset,
 193                  debugtest=False, name=None):
 194         super().__init__(rwid)
 195         self.awid = awid
 196         self.pi = pi
 197         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name)
 198         self.debugtest = debugtest # enable debug output for unit testing
 199
 200         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 201         self.n_src = n_src = 3   # RA, RB, RT/RS
 202         self.n_dst = n_dst = 3  # RA, RT/RS, CR0
 203
 204         # set up array of src and dest signals
 205         for i in range(n_src):
 206             j = i + 1  # name numbering to match src1/src2
 207             name = "src%d_i" % j
 208             setattr(self, name, getattr(cu, name))
 209
 210         dst = []
 211         for i in range(n_dst):
 212             j = i + 1  # name numbering to match dest1/2...
 213             name = "dest%d_o" % j
 214             setattr(self, name, getattr(cu, name))
 215
 216         # convenience names
 217         self.rd = cu.rd
 218         self.wr = cu.wr
 219         self.rdmaskn = cu.rdmaskn
 220         self.wrmask = cu.wrmask
 221         self.ad = cu.ad
 222         self.st = cu.st
 223         self.dest = cu._dest
 224
 225         # HACK: get data width from dest[0].  this is used across the board
 226         # (it really shouldn't be)
 227         self.data_wid = self.dest[0].shape()
 228
 229         self.go_rd_i = self.rd.go_i  # temporary naming
 230         self.go_wr_i = self.wr.go_i  # temporary naming
 231         self.go_ad_i = self.ad.go_i  # temp naming: go address in
 232         self.go_st_i = self.st.go_i  # temp naming: go store in
 233
 234         self.rd_rel_o = self.rd.rel_o  # temporary naming
 235         self.req_rel_o = self.wr.rel_o  # temporary naming
 236         self.adr_rel_o = self.ad.rel_o  # request address (from mem)
 237         self.sto_rel_o = self.st.rel_o  # request store (to mem)
 238
 239         self.issue_i = cu.issue_i
 240         self.shadown_i = cu.shadown_i
 241         self.go_die_i = cu.go_die_i
 242
 243         self.oper_i = cu.oper_i
 244         self.src_i = cu._src_i
 245
 246         self.o_data = Data(self.data_wid, name="o")  # Dest1 out: RT
 247         self.addr_o = Data(self.data_wid, name="ea")  # Addr out: Update => RA
 248         self.cr_o = Data(4, name="cr0")  # CR0 (for stdcx etc)
 249         self.exc_o = cu.exc_o
 250         self.done_o = cu.done_o
 251         self.busy_o = cu.busy_o
 252
 253         self.ld_o = cu.ld_o
 254         self.st_o = cu.st_o
 255
 256         self.load_mem_o = cu.load_mem_o
 257         self.stwd_mem_o = cu.stwd_mem_o
 258
 259     def elaborate(self, platform):
 260         m = Module()
 261
 262         # temp/convenience
 263         comb = m.d.comb
 264         sync = m.d.sync
 265         issue_i = self.issue_i
 266
 267         #####################
 268         # latches for the FSM.
 269         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 270         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 271         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 272         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 273         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 274         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 275         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 276         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 277         m.submodules.cr0_l = cr0_l = SRLatch(sync=False, name="cr0")
 278         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 279         m.submodules.lsd_l = lsd_l = SRLatch(sync=False, name="lsd") # done
 280
 281         ####################
 282         # signals
 283
 284         # opcode decode
 285         op_is_ld = Signal(reset_less=True)
 286         op_is_st = Signal(reset_less=True)
 287         op_is_dcbz = Signal(reset_less=True)
 288         op_is_st_or_dcbz = Signal(reset_less=True)
 289         op_is_atomic = Signal(reset_less=True)
 290
 291         # ALU/LD data output control
 292         alu_valid = Signal(reset_less=True)  # ALU operands are valid
 293         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 294         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 295         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 296         wr_any = Signal(reset_less=True)    # any write (incl. store)
 297         rda_any = Signal(reset_less=True)   # any read for address ops
 298         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 299         wr_reset = Signal(reset_less=True)  # final reset condition
 300         canceln = Signal(reset_less=True)   # cancel (active low)
 301         store_done = Signal(reset_less=True) # store has been actioned
 302
 303         # LD and ALU out
 304         alu_o = Signal(self.data_wid, reset_less=True)
 305         ldd_o = Signal(self.data_wid, reset_less=True)
 306
 307         ##############################
 308         # reset conditions for latches
 309
 310         # temporaries (also convenient when debugging)
 311         reset_o = Signal(reset_less=True)             # reset opcode
 312         reset_w = Signal(reset_less=True)             # reset write
 313         reset_u = Signal(reset_less=True)             # reset update
 314         reset_c = Signal(reset_less=True)             # reset cr0
 315         reset_a = Signal(reset_less=True)             # reset adr latch
 316         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 317         reset_r = Signal(self.n_src, reset_less=True)  # reset src
 318         reset_s = Signal(reset_less=True)             # reset store
 319
 320         # end execution when a terminating condition is detected:
 321         # - go_die_i: a speculative operation was cancelled
 322         # - exc_o.happened: an exception has occurred
 323         terminate = Signal()
 324         comb += terminate.eq(self.go_die_i | self.exc_o.happened)
 325
 326         comb += reset_i.eq(issue_i | terminate)       # various
 327         comb += reset_o.eq(self.done_o | terminate)      # opcode reset
 328         comb += reset_w.eq(self.wr.go_i[0] | terminate)  # write reg 1
 329         comb += reset_u.eq(self.wr.go_i[1] | terminate)  # update (reg 2)
 330         comb += reset_c.eq(self.wr.go_i[2] | terminate)  # cr0 (reg 3)
 331         comb += reset_s.eq(self.go_st_i | terminate)  # store reset
 332         comb += reset_r.eq(self.rd.go_i | Repl(terminate, self.n_src))
 333         comb += reset_a.eq(self.go_ad_i | terminate)
 334
 335         p_st_go = Signal(reset_less=True)
 336         sync += p_st_go.eq(self.st.go_i)
 337
 338         # decode bits of operand (latched)
 339         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 340         comb += op_is_st.eq(oper_r.insn_type == MicrOp.OP_STORE)   # ST
 341         comb += op_is_ld.eq(oper_r.insn_type == MicrOp.OP_LOAD)    # LD
 342         comb += op_is_dcbz.eq(oper_r.insn_type == MicrOp.OP_DCBZ)  # DCBZ
 343         comb += op_is_atomic.eq(oper_r.reserve) # atomic LR/SC
 344         comb += op_is_st_or_dcbz.eq(op_is_st | op_is_dcbz)
 345         # dcbz is special case of store
 346         #uncomment if needed
 347         #comb += Display("compldst_multi: op_is_dcbz = %i",
 348         #                (oper_r.insn_type == MicrOp.OP_DCBZ))
 349         op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
 350         op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
 351         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 352         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 353         comb += self.ld_o.eq(op_is_ld)
 354         comb += self.st_o.eq(op_is_st)
 355
 356         ##########################
 357         # FSM implemented through sequence of latches.  approximately this:
 358         # - opc_l       : opcode
 359         #    - src_l[0] : operands
 360         #    - src_l[1]
 361         #       - alu_l : looks after add of src1/2/imm (EA)
 362         #       - adr_l : waits for add (EA)
 363         #       - upd_l : waits for adr and Regfile (port 2)
 364         #       - cr0_l : waits for Rc=1 and CR0 Regfile (port 3)
 365         #    - src_l[2] : ST
 366         # - lod_l       : waits for adr (EA) and for LD Data
 367         # - wri_l       : waits for LD Data and Regfile (port 1)
 368         # - st_l        : waits for alu and operand2
 369         # - rst_l       : waits for all FSM paths to converge.
 370         # NOTE: use sync to stop combinatorial loops.
 371
 372         # opcode latch - inverted so that busy resets to 0
 373         # note this MUST be sync so as to avoid a combinatorial loop
 374         # between busy_o and issue_i on the reset latch (rst_l)
 375         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 376         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 377
 378         # src operand latch
 379         sync += src_l.s.eq(Repl(issue_i, self.n_src) & ~self.rdmaskn)
 380         sync += src_l.r.eq(reset_r)
 381         #### sync += Display("reset_r = %i",reset_r)
 382
 383         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 384         comb += alu_l.s.eq(reset_i)
 385         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 386
 387         # addr latch
 388         comb += adr_l.s.eq(reset_i)
 389         sync += adr_l.r.eq(reset_a)
 390
 391         # ld latch
 392         comb += lod_l.s.eq(reset_i)
 393         comb += lod_l.r.eq(ld_ok)
 394
 395         # dest operand latch
 396         comb += wri_l.s.eq(issue_i)
 397         sync += wri_l.r.eq(reset_w | Repl(wr_reset |
 398                                           (~self.pi.busy_o & op_is_update),
 399                                           #(self.pi.busy_o & op_is_update),
 400                             #self.done_o | (self.pi.busy_o & op_is_update),
 401                                           self.n_dst))
 402
 403         # CR0 operand latch (CR0 written to reg 3 if Rc=1)
 404         op_is_rc1 = self.oper_i.rc.rc & self.oper_i.rc.ok
 405         comb += cr0_l.s.eq(issue_i & op_is_rc1)
 406         sync += cr0_l.r.eq(reset_c)
 407
 408         # update-mode operand latch (EA written to reg 2)
 409         sync += upd_l.s.eq(reset_i)
 410         sync += upd_l.r.eq(reset_u)
 411
 412         # store latch
 413         comb += sto_l.s.eq(addr_ok & op_is_st_or_dcbz)
 414         sync += sto_l.r.eq(reset_s | p_st_go)
 415
 416         # ld/st done.  needed to stop LD/ST from activating repeatedly
 417         comb += lsd_l.s.eq(issue_i)
 418         sync += lsd_l.r.eq(reset_s | p_st_go | ld_ok)
 419
 420         # reset latch
 421         comb += rst_l.s.eq(addr_ok)  # start when address is ready
 422         comb += rst_l.r.eq(issue_i)
 423
 424         # create a latch/register for the operand
 425         with m.If(self.issue_i):
 426             sync += oper_r.eq(self.oper_i)
 427         with m.If(self.done_o | terminate):
 428             sync += oper_r.eq(0)
 429
 430         # and for LD and store-done
 431         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
 432         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 433
 434         # store actioned, communicate through CR0 (for atomic LR/SC)
 435         latchregister(m, self.pi.store_done.data, store_done,
 436                          self.pi.store_done.ok,
 437                          name="std_r")
 438
 439         # and for each input from the incoming src operands
 440         srl = []
 441         for i in range(self.n_src):
 442             name = "src_r%d" % i
 443             src_r = Signal(self.data_wid, name=name, reset_less=True)
 444             with m.If(self.rd.go_i[i]):
 445                 sync += src_r.eq(self.src_i[i])
 446             with m.If(self.issue_i):
 447                 sync += src_r.eq(0)
 448             srl.append(src_r)
 449
 450         # and one for the output from the ADD (for the EA)
 451         addr_r = Signal(self.data_wid, reset_less=True)  # Effective Address
 452         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 453
 454         # select either zero or src1 if opcode says so
 455         op_is_z = oper_r.zero_a
 456         src1_or_z = Signal(self.data_wid, reset_less=True)
 457         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 458
 459         # select either immediate or src2 if opcode says so
 460         op_is_imm = oper_r.imm_data.ok
 461         src2_or_imm = Signal(self.data_wid, reset_less=True)
 462         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.data, srl[1]))
 463
 464         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 465         comb += alu_o.eq(src1_or_z + src2_or_imm)  # actual EA
 466         m.d.sync += alu_ok.eq(alu_valid & canceln) # keep ack in sync with EA
 467
 468         ############################
 469         # Control Signal calculation
 470
 471         # busy signal
 472         busy_o = self.busy_o
 473         comb += self.busy_o.eq(opc_l.q)  # | self.pi.busy_o)  # busy out
 474
 475         # 1st operand read-request only when zero not active
 476         # 2nd operand only needed when immediate is not active
 477         slg = Cat(op_is_z, op_is_imm) #is this correct ?
 478         bro = Repl(self.busy_o, self.n_src)
 479         comb += self.rd.rel_o.eq(src_l.q & bro & ~slg)
 480
 481         # note when the address-related read "go" signals are active
 482         comb += rda_any.eq(self.rd.go_i[0] | self.rd.go_i[1])
 483
 484         # alu input valid when 1st and 2nd ops done (or imm not active)
 485         comb += alu_valid.eq(busy_o & ~(self.rd.rel_o[0] | self.rd.rel_o[1]) &
 486                              canceln)
 487
 488         # 3rd operand only needed when operation is a store
 489         comb += self.rd.rel_o[2].eq(src_l.q[2] & busy_o & op_is_st)
 490
 491         # all reads done when alu is valid and 3rd operand needed
 492         comb += rd_done.eq(alu_valid & ~self.rd.rel_o[2])
 493
 494         # address release only if addr ready, but Port must be idle
 495         comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 496
 497         # the write/store (etc) all must be cancelled if an exception occurs
 498         # note: cancel is active low, like shadown_i,
 499         #       while exc_o.happpened is active high
 500         comb += canceln.eq(~self.exc_o.happened & self.shadown_i)
 501
 502         # store release when st ready *and* all operands read (and no shadow)
 503         # dcbz is special case of store -- TODO verify shadows
 504         comb += self.st.rel_o.eq(sto_l.q & busy_o & rd_done & op_is_st_or_dcbz &
 505                                canceln)
 506
 507         # request write of LD result.  waits until shadow is dropped.
 508         comb += self.wr.rel_o[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
 509                                   op_is_ld & canceln)
 510
 511         # request write of EA result only in update mode
 512         comb += self.wr.rel_o[1].eq(upd_l.q & busy_o & op_is_update &
 513                                   alu_valid & canceln)
 514
 515         # request write of CR0 result only in reserve and Rc=1
 516         comb += self.wr.rel_o[2].eq(cr0_l.q & busy_o & op_is_atomic &
 517                                   alu_valid & canceln)
 518
 519         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 520         comb += wr_any.eq(self.st.go_i | p_st_go |
 521                           self.wr.go_i.bool())
 522         comb += wr_reset.eq(rst_l.q & busy_o & canceln &
 523                             ~(self.st.rel_o | self.wr.rel_o.bool()) &
 524                             (lod_l.qn | op_is_st_or_dcbz)
 525                             )
 526         comb += self.done_o.eq(wr_reset & (~self.pi.busy_o | op_is_ld))
 527
 528         ######################
 529         # Data/Address outputs
 530
 531         # put the LD-output register directly onto the output bus on a go_write
 532         comb += self.o_data.data.eq(self.dest[0])
 533         comb += self.o_data.ok.eq(self.wr.rel_o[0])
 534         with m.If(self.wr.go_i[0]):
 535             comb += self.dest[0].eq(ldd_r)
 536
 537         # "update" mode, put address out on 2nd go-write
 538         comb += self.addr_o.data.eq(self.dest[1])
 539         comb += self.addr_o.ok.eq(self.wr.rel_o[1])
 540         with m.If(op_is_update & self.wr.go_i[1]):
 541             comb += self.dest[1].eq(addr_r)
 542
 543         # fun-fun-fun, calculate CR0 when Rc=1 requested.
 544         cr0 = self.dest[2]
 545         comb += self.cr_o.data.eq(cr0)
 546         comb += self.cr_o.ok.eq(self.wr.rel_o[2])
 547         with m.If(cr0_l.q):
 548             comb += cr0.eq(Cat(C(0, 1), store_done, C(0, 2)))
 549
 550         # need to look like MultiCompUnit: put wrmask out.
 551         # XXX may need to make this enable only when write active
 552         comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update, cr0_l.q))
 553
 554         ###########################
 555         # PortInterface connections
 556         pi = self.pi
 557
 558         # connect to LD/ST PortInterface.
 559         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 560         comb += pi.is_st_i.eq(op_is_st_or_dcbz & busy_o)  # decoded-ST
 561         comb += pi.is_dcbz_i.eq(op_is_dcbz & busy_o)  # decoded-DCBZ
 562         comb += pi.reserve.eq(oper_r.reserve & busy_o)  # atomic LR/SC
 563         comb += pi.data_len.eq(oper_r.data_len)  # data_len
 564         # address: use sync to avoid long latency
 565         sync += pi.addr.data.eq(addr_r)           # EA from adder
 566         with m.If(op_is_dcbz):
 567             sync += Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r)
 568
 569         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
 570         comb += self.exc_o.eq(pi.exc_o)  # exception occurred
 571         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 572         # connect MSR.PR etc. for priv/virt operation
 573         comb += pi.priv_mode.eq(~oper_r.msr[MSR.PR])
 574         comb += pi.virt_mode.eq(oper_r.msr[MSR.DR])
 575         comb += pi.mode_32bit.eq(~oper_r.msr[MSR.SF])
 576         with m.If(self.issue_i): # display this only once
 577             sync += Display("LDSTCompUnit: oper_r.msr %x pr=%x dr=%x sf=%x",
 578                                       oper_r.msr,
 579                                       oper_r.msr[MSR.PR],
 580                                       oper_r.msr[MSR.DR],
 581                                       oper_r.msr[MSR.SF])
 582
 583         # byte-reverse on LD
 584         revnorev = Signal(64, reset_less=True)
 585         with m.If(oper_r.byte_reverse):
 586             # byte-reverse the data based on ld/st width (turn it to LE)
 587             data_len = oper_r.data_len
 588             lddata_r = byte_reverse(m, 'lddata_r', pi.ld.data, data_len)
 589             comb += revnorev.eq(lddata_r)  # put reversed- data out
 590         with m.Else():
 591             comb += revnorev.eq(pi.ld.data)  # put data out, straight (as BE)
 592
 593         # then check sign-extend
 594         with m.If(oper_r.sign_extend):
 595             # okok really should "if data_len == 4" and so on here
 596             with m.If(oper_r.data_len == 2):
 597                 comb += ldd_o.eq(exts(revnorev, 16, 64))  # sign-extend hword
 598             with m.Else():
 599                 comb += ldd_o.eq(exts(revnorev, 32, 64))  # sign-extend dword
 600         with m.Else():
 601             comb += ldd_o.eq(revnorev)
 602
 603         # ld - ld gets latched in via lod_l
 604         comb += ld_ok.eq(pi.ld.ok)  # ld.ok *closes* (freezes) ld data
 605
 606         # byte-reverse on ST
 607         op3 = srl[2] # 3rd operand latch
 608         with m.If(oper_r.byte_reverse):
 609             # byte-reverse the data based on width
 610             data_len = oper_r.data_len
 611             stdata_r = byte_reverse(m, 'stdata_r', op3, data_len)
 612             comb += pi.st.data.eq(stdata_r)
 613         with m.Else():
 614             comb += pi.st.data.eq(op3)
 615
 616         # store - data goes in based on go_st
 617         comb += pi.st.ok.eq(self.st.go_i)  # go store signals st data valid
 618
 619         return m
 620
 621     def get_out(self, i):
 622         """make LDSTCompUnit look like RegSpecALUAPI.  these correspond
 623         to LDSTOutputData o and o1 respectively.
 624         """
 625         if i == 0:
 626             return self.o_data # LDSTOutputData.regspec o
 627         if i == 1:
 628             return self.addr_o # LDSTOutputData.regspec o1
 629         if i == 2:
 630             return self.cr_o # LDSTOutputData.regspec cr_a
 631         # return self.dest[i]
 632
 633     def get_fu_out(self, i):
 634         return self.get_out(i)
 635
 636     def __iter__(self):
 637         yield self.rd.go_i
 638         yield self.go_ad_i
 639         yield self.wr.go_i
 640         yield self.go_st_i
 641         yield self.issue_i
 642         yield self.shadown_i
 643         yield self.go_die_i
 644         yield from self.oper_i.ports()
 645         yield from self.src_i
 646         yield self.busy_o
 647         yield self.rd.rel_o
 648         yield self.adr_rel_o
 649         yield self.sto_rel_o
 650         yield self.wr.rel_o
 651         yield from self.o_data.ports()
 652         yield from self.addr_o.ports()
 653         yield from self.cr_o.ports()
 654         yield self.load_mem_o
 655         yield self.stwd_mem_o
 656
 657     def ports(self):
 658         return list(self)
 659
 660
 661 def wait_for(sig, wait=True, test1st=False):
 662     v = (yield sig)
 663     print("wait for", sig, v, wait, test1st)
 664     if test1st and bool(v) == wait:
 665         return
 666     while True:
 667         yield
 668         v = (yield sig)
 669         #print("...wait for", sig, v)
 670         if bool(v) == wait:
 671             break
 672
 673
 674 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False,
 675           byterev=True):
 676     print("ST", src1, src2, src3, imm, imm_ok, update)
 677     yield dut.oper_i.insn_type.eq(MicrOp.OP_STORE)
 678     yield dut.oper_i.data_len.eq(2)  # half-word
 679     yield dut.oper_i.byte_reverse.eq(byterev)
 680     yield dut.src1_i.eq(src1)
 681     yield dut.src2_i.eq(src2)
 682     yield dut.src3_i.eq(src3)
 683     yield dut.oper_i.imm_data.data.eq(imm)
 684     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 685     #guess: this one was removed -- yield dut.oper_i.update.eq(update)
 686     yield dut.issue_i.eq(1)
 687     yield
 688     yield dut.issue_i.eq(0)
 689
 690     if imm_ok:
 691         active_rel = 0b101
 692     else:
 693         active_rel = 0b111
 694     # wait for all active rel signals to come up
 695     while True:
 696         rel = yield dut.rd.rel_o
 697         if rel == active_rel:
 698             break
 699         yield
 700     yield dut.rd.go_i.eq(active_rel)
 701     yield
 702     yield dut.rd.go_i.eq(0)
 703
 704     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 705     # yield from wait_for(dut.adr_rel_o)
 706     # yield dut.ad.go.eq(1)
 707     # yield
 708     # yield dut.ad.go.eq(0)
 709
 710     if update:
 711         yield from wait_for(dut.wr.rel_o[1])
 712         yield dut.wr.go.eq(0b10)
 713         yield
 714         addr = yield dut.addr_o
 715         print("addr", addr)
 716         yield dut.wr.go.eq(0)
 717     else:
 718         addr = None
 719
 720     yield from wait_for(dut.sto_rel_o)
 721     yield dut.go_st_i.eq(1)
 722     yield
 723     yield dut.go_st_i.eq(0)
 724     yield from wait_for(dut.busy_o, False)
 725     # wait_for(dut.stwd_mem_o)
 726     yield
 727     return addr
 728
 729
 730 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
 731          byterev=True):
 732     print("LD", src1, src2, imm, imm_ok, update)
 733     yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
 734     yield dut.oper_i.data_len.eq(2)  # half-word
 735     yield dut.oper_i.byte_reverse.eq(byterev)
 736     yield dut.src1_i.eq(src1)
 737     yield dut.src2_i.eq(src2)
 738     yield dut.oper_i.zero_a.eq(zero_a)
 739     yield dut.oper_i.imm_data.data.eq(imm)
 740     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 741     yield dut.issue_i.eq(1)
 742     yield
 743     yield dut.issue_i.eq(0)
 744     yield
 745
 746     # set up read-operand flags
 747     rd = 0b00
 748     if not imm_ok:  # no immediate means RB register needs to be read
 749         rd |= 0b10
 750     if not zero_a:  # no zero-a means RA needs to be read
 751         rd |= 0b01
 752
 753     # wait for the operands (RA, RB, or both)
 754     if rd:
 755         yield dut.rd.go_i.eq(rd)
 756         yield from wait_for(dut.rd.rel_o)
 757         yield dut.rd.go_i.eq(0)
 758
 759     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 760     # yield dut.ad.go.eq(1)
 761     # yield
 762     # yield dut.ad.go.eq(0)
 763
 764     if update:
 765         yield from wait_for(dut.wr.rel_o[1])
 766         yield dut.wr.go_i.eq(0b10)
 767         yield
 768         addr = yield dut.addr_o
 769         print("addr", addr)
 770         yield dut.wr.go_i.eq(0)
 771     else:
 772         addr = None
 773
 774     yield from wait_for(dut.wr.rel_o[0], test1st=True)
 775     yield dut.wr.go_i.eq(1)
 776     yield
 777     data = yield dut.o_data.o
 778     data_ok = yield dut.o_data.o_ok
 779     yield dut.wr.go_i.eq(0)
 780     yield from wait_for(dut.busy_o)
 781     yield
 782     # wait_for(dut.stwd_mem_o)
 783     return data, data_ok, addr
 784
 785
 786 def ldst_sim(dut):
 787
 788     ###################
 789     # immediate version
 790
 791     # two STs (different addresses)
 792     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 793     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 794     yield
 795     # two LDs (deliberately LD from the 1st address then 2nd)
 796     data, addr = yield from load(dut, 4, 0, 2)
 797     assert data == 0x0003, "returned %x" % data
 798     data, addr = yield from load(dut, 2, 0, 2)
 799     assert data == 0x0009, "returned %x" % data
 800     yield
 801
 802     # indexed version
 803     yield from store(dut, 9, 5, 3, 0, imm_ok=False)
 804     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
 805     assert data == 0x0003, "returned %x" % data
 806
 807     # update-immediate version
 808     addr = yield from store(dut, 9, 6, 3, 2, update=True)
 809     assert addr == 0x000b, "returned %x" % addr
 810
 811     # update-indexed version
 812     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
 813     assert data == 0x0003, "returned %x" % data
 814     assert addr == 0x000e, "returned %x" % addr
 815
 816     # immediate *and* zero version
 817     data, addr = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
 818     assert data == 0x0008, "returned %x" % data
 819
 820
 821 class TestLDSTCompUnit(LDSTCompUnit):
 822
 823     def __init__(self, rwid, pspec):
 824         from soc.experiment.l0_cache import TstL0CacheBuffer
 825         self.l0 = l0 = TstL0CacheBuffer(pspec)
 826         pi = l0.l0.dports[0]
 827         LDSTCompUnit.__init__(self, pi, rwid, 4)
 828
 829     def elaborate(self, platform):
 830         m = LDSTCompUnit.elaborate(self, platform)
 831         m.submodules.l0 = self.l0
 832         # link addr-go direct to rel
 833         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 834         return m
 835
 836
 837 def test_scoreboard():
 838
 839     units = {}
 840     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 841                          imem_ifacetype='bare_wb',
 842                          addr_wid=64,
 843                          mask_wid=8,
 844                          reg_wid=64,
 845                          units=units)
 846
 847     dut = TestLDSTCompUnit(16,pspec)
 848     vl = rtlil.convert(dut, ports=dut.ports())
 849     with open("test_ldst_comp.il", "w") as f:
 850         f.write(vl)
 851
 852     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 853
 854
 855 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 856
 857     def __init__(self, pspec):
 858         from soc.experiment.l0_cache import TstL0CacheBuffer
 859         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 860         regspec = LDSTPipeSpec.regspec
 861         self.l0 = l0 = TstL0CacheBuffer(pspec)
 862         pi = l0.l0.dports[0]
 863         LDSTCompUnit.__init__(self, pi, regspec, 4)
 864
 865     def elaborate(self, platform):
 866         m = LDSTCompUnit.elaborate(self, platform)
 867         m.submodules.l0 = self.l0
 868         # link addr-go direct to rel
 869         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 870         return m
 871
 872
 873 def test_scoreboard_regspec():
 874
 875     units = {}
 876     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 877                          imem_ifacetype='bare_wb',
 878                          addr_wid=64,
 879                          mask_wid=8,
 880                          reg_wid=64,
 881                          units=units)
 882
 883     dut = TestLDSTCompUnitRegSpec(pspec)
 884     vl = rtlil.convert(dut, ports=dut.ports())
 885     with open("test_ldst_comp.il", "w") as f:
 886         f.write(vl)
 887
 888     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 889
 890
 891 if __name__ == '__main__':
 892     test_scoreboard_regspec()
 893     test_scoreboard()