src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 Both LD and ST may request that the address be computed from summing
  24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25 the immediate (from the opcode).
  26
  27 Both LD and ST may also request "update" mode (op_is_update) which
  28 activates the use of Go_Write[1] to control storage of the EA into
  29 a *second* operand in the register file.
  30
  31 Thus this module has *TWO* write-requests to the register file and
  32 *THREE* read-requests to the register file (not all at the same time!)
  33 The regfile port usage is:
  34
  35 * LD-imm         1R1W
  36 * LD-imm-update  1R2W
  37 * LD-idx         2R1W
  38 * LD-idx-update  2R2W
  39
  40 * ST-imm         2R
  41 * ST-imm-update  2R1W
  42 * ST-idx         3R
  43 * ST-idx-update  3R1W
  44
  45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47 the nested FSMs below are *combinatorial*).
  48
  49 * One FSM covers Operand collection and communication address-side
  50   with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52 * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54 * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56 * The "overall" (fourth) FSM coordinates the progression and completion
  57   of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59 Full diagram:
  60 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  61
  62 Links including to walk-through videos:
  63 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  64 * http://libre-soc.org/openpower/isa/fixedload
  65 * http://libre-soc.org/openpower/isa/fixedstore
  66
  67 Related Bugreports:
  68 * https://bugs.libre-soc.org/show_bug.cgi?id=302
  69
  70 Terminology:
  71
  72 * EA - Effective Address
  73 * LD - Load
  74 * ST - Store
  75 """
  76
  77 from nmigen.compat.sim import run_simulation
  78 from nmigen.cli import verilog, rtlil
  79 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  80 from nmigen.hdl.rec import Record, Layout
  81
  82 from nmutil.latch import SRLatch, latchregister
  83
  84 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  85 from soc.experiment.l0_cache import PortInterface
  86 from soc.experiment.testmem import TestMemory
  87
  88 from soc.decoder.power_enums import InternalOp, Function
  89 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  90
  91
  92 class LDSTCompUnitRecord(CompUnitRecord):
  93     def __init__(self, rwid, name=None):
  94         CompUnitRecord.__init__(self, CompLDSTOpSubset, rwid,
  95                                 n_src=3, n_dst=2, name=name)
  96
  97         self.ad = go_record(1, name="ad") # address go in, req out
  98         self.st = go_record(1, name="st") # store go in, req out
  99
 100         self.addr_exc_o = Signal(reset_less=True)   # address exception
 101
 102         self.ld_o = Signal(reset_less=True)  # operation is a LD
 103         self.st_o = Signal(reset_less=True)  # operation is a ST
 104
 105         # hmm... are these necessary?
 106         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 107         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 108
 109
 110 class LDSTCompUnit(Elaboratable):
 111     """LOAD / STORE Computation Unit
 112
 113     Inputs
 114     ------
 115
 116     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 117     * :rwid:   register width
 118     * :awid:   address width
 119
 120     Data inputs
 121     -----------
 122     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 123
 124     Data (outputs)
 125     --------------
 126     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 127     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 128     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 129
 130     TODO: make addr_exc_o a data-type rather than a single-bit signal
 131           (see bug #302)
 132
 133     Control Signals (In)
 134     --------------------
 135
 136     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 137     * :issue_i:    LD/ST is being "issued".
 138     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 139     * :go_rd_i:    read is being actioned (latches in src regs)
 140     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 141     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 142     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 143     * :go_die_i:   resets the unit back to "wait for issue"
 144
 145     Control Signals (Out)
 146     ---------------------
 147
 148     * :busy_o:      function unit is busy
 149     * :rd_rel_o:    request src1/src2
 150     * :adr_rel_o:   request address (from mem)
 151     * :sto_rel_o:   request store (to mem)
 152     * :req_rel_o:   request write (result)
 153     * :load_mem_o:  activate memory LOAD
 154     * :stwd_mem_o:  activate memory STORE
 155
 156     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 157     in a single cycle and the CompUnit set back to doing another op.
 158     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 159     depending on whether the operation is a ST or LD.
 160     """
 161
 162     def __init__(self, pi=None, rwid=64, awid=48, debugtest=False):
 163         self.rwid = rwid
 164         self.awid = awid
 165         self.pi = pi
 166         self.cu = cu = LDSTCompUnitRecord(rwid)
 167         self.debugtest = debugtest
 168
 169         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 170         self.n_src = n_src = 3   # RA, RB, RT/RS
 171         self.n_dst = n_dst = 2 # RA, RT/RS
 172
 173         # set up array of src and dest signals
 174         for i in range(n_src):
 175             j = i + 1 # name numbering to match src1/src2
 176             name = "src%d_i" % j
 177             setattr(self, name, getattr(cu, name))
 178
 179         dst = []
 180         for i in range(n_dst):
 181             j = i + 1 # name numbering to match dest1/2...
 182             name = "dest%d_o" % j
 183             setattr(self, name, getattr(cu, name))
 184
 185         # convenience names
 186         self.rd = cu.rd
 187         self.wr = cu.wr
 188         self.ad = cu.ad
 189         self.st = cu.st
 190
 191         self.go_rd_i = self.rd.go # temporary naming
 192         self.go_wr_i = self.wr.go # temporary naming
 193         self.go_ad_i = self.ad.go # temp naming: go address in
 194         self.go_st_i = self.st.go  # temp naming: go store in
 195
 196         self.rd_rel_o = self.rd.rel # temporary naming
 197         self.req_rel_o = self.wr.rel # temporary naming
 198         self.adr_rel_o = self.ad.rel  # request address (from mem)
 199         self.sto_rel_o = self.st.rel  # request store (to mem)
 200
 201         self.issue_i = cu.issue_i
 202         self.shadown_i = cu.shadown_i
 203         self.go_die_i = cu.go_die_i
 204
 205         self.oper_i = cu.oper_i
 206         self.src_i = cu._src_i
 207         self.dest = cu._dest
 208
 209         self.data_o = self.dest[0]  # Dest1 out: RT
 210         self.addr_o = self.dest[1]  # Address out (LD or ST) - Update => RA
 211         self.addr_exc_o = cu.addr_exc_o
 212         self.done_o = cu.done_o
 213         self.busy_o = cu.busy_o
 214
 215         self.ld_o = cu.ld_o
 216         self.st_o = cu.st_o
 217
 218         self.load_mem_o = cu.load_mem_o
 219         self.stwd_mem_o = cu.stwd_mem_o
 220
 221     def elaborate(self, platform):
 222         m = Module()
 223
 224         # temp/convenience
 225         comb = m.d.comb
 226         sync = m.d.sync
 227         issue_i = self.issue_i
 228
 229         #####################
 230         # latches for the FSM.
 231         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 232         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 233         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 234         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 235         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 236         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 237         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 238         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 239         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 240
 241         ####################
 242         # signals
 243
 244         # opcode decode
 245         op_is_ld = Signal(reset_less=True)
 246         op_is_st = Signal(reset_less=True)
 247
 248         # ALU/LD data output control
 249         alu_valid = Signal(reset_less=True) # ALU operands are valid
 250         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 251         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 252         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 253         wr_any = Signal(reset_less=True)    # any write (incl. store)
 254         rda_any = Signal(reset_less=True)   # any read for address ops
 255         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 256         wr_reset = Signal(reset_less=True)  # final reset condition
 257
 258         # LD and ALU out
 259         alu_o = Signal(self.rwid, reset_less=True)
 260         ldd_o = Signal(self.rwid, reset_less=True)
 261
 262         # XXX TODO ZEROing just like in CompUnit
 263
 264
 265         ##############################
 266         # reset conditions for latches
 267
 268         # temporaries (also convenient when debugging)
 269         reset_o = Signal(reset_less=True)             # reset opcode
 270         reset_w = Signal(reset_less=True)             # reset write
 271         reset_u = Signal(reset_less=True)             # reset update
 272         reset_a = Signal(reset_less=True)             # reset adr latch
 273         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 274         reset_r = Signal(self.n_src, reset_less=True) # reset src
 275         reset_s = Signal(reset_less=True)             # reset store
 276
 277         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 278         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 279         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 280         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 281         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 282         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 283         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 284
 285         ##########################
 286         # FSM implemented through sequence of latches.  approximately this:
 287         # - opc_l       : opcode
 288         #    - src_l[0] : operands
 289         #    - src_l[1]
 290         #       - alu_l : looks after add of src1/2/imm (EA)
 291         #       - adr_l : waits for add (EA)
 292         #       - upd_l : waits for adr and Regfile (port 2)
 293         #    - src_l[2] : ST
 294         # - lod_l       : waits for adr (EA) and for LD Data
 295         # - wri_l       : waits for LD Data and Regfile (port 1)
 296         # - st_l        : waits for alu and operand2
 297         # - rst_l       : waits for all FSM paths to converge.
 298         # NOTE: use sync to stop combinatorial loops.
 299
 300         # opcode latch - inverted so that busy resets to 0
 301         # note this MUST be sync so as to avoid a combinatorial loop
 302         # between busy_o and issue_i on the reset latch (rst_l)
 303         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 304         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 305
 306         # src operand latch
 307         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 308         sync += src_l.r.eq(reset_r)
 309
 310         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 311         comb += alu_l.s.eq(reset_i)
 312         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 313
 314         # addr latch
 315         comb += adr_l.s.eq(reset_i)
 316         sync += adr_l.r.eq(reset_a)
 317
 318         # ld latch
 319         comb += lod_l.s.eq(reset_i)
 320         comb += lod_l.r.eq(ld_ok)
 321
 322         # dest operand latch
 323         comb += wri_l.s.eq(issue_i)
 324         sync += wri_l.r.eq(reset_w)
 325
 326         # update-mode operand latch (EA written to reg 2)
 327         sync += upd_l.s.eq(reset_i)
 328         sync += upd_l.r.eq(reset_u)
 329
 330         # store latch
 331         comb += sto_l.s.eq(addr_ok & op_is_st)
 332         comb += sto_l.r.eq(reset_s)
 333
 334         # reset latch
 335         comb += rst_l.s.eq(addr_ok) # start when address is ready
 336         comb += rst_l.r.eq(issue_i)
 337
 338         # create a latch/register for the operand
 339         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 340         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 341
 342         # and for LD
 343         ldd_r = Signal(self.rwid, reset_less=True)  # Dest register
 344         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 345
 346         # and for each input from the incoming src operands
 347         srl = []
 348         for i in range(self.n_src):
 349             name = "src_r%d" % i
 350             src_r = Signal(self.rwid, name=name, reset_less=True)
 351             latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
 352             srl.append(src_r)
 353
 354         # and one for the output from the ADD (for the EA)
 355         addr_r = Signal(self.rwid, reset_less=True)  # Effective Address Latch
 356         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 357
 358         # select either zero or src1 if opcode says so
 359         op_is_z = oper_r.zero_a
 360         src1_or_z = Signal(self.rwid, reset_less=True)
 361         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 362
 363         # select either immediate or src2 if opcode says so
 364         op_is_imm = oper_r.imm_data.imm_ok
 365         src2_or_imm = Signal(self.rwid, reset_less=True)
 366         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 367
 368         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 369         sync += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
 370         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 371
 372         # decode bits of operand (latched)
 373         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 374         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 375         op_is_update = oper_r.update                                 # UPDATE
 376         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 377         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 378         comb += self.ld_o.eq(op_is_ld)
 379         comb += self.st_o.eq(op_is_st)
 380
 381         ############################
 382         # Control Signal calculation
 383
 384         # busy signal
 385         busy_o = self.busy_o
 386         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 387
 388         # 1st operand read-request only when zero not active
 389         comb += self.rd.rel[0].eq(src_l.q[0] & busy_o & ~op_is_z)
 390
 391         # 2nd operand only needed when immediate is not active
 392         comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
 393
 394         # note when the address-related read "go" signals are active
 395         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 396
 397         # alu input valid when 1st and 2nd ops done (or imm not active)
 398         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 399
 400         # 3rd operand only needed when operation is a store
 401         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 402
 403         # all reads done when alu is valid and 3rd operand needed
 404         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 405
 406         # address release only if addr ready, but Port must be idle
 407         comb += self.adr_rel_o.eq(adr_l.q & busy_o)
 408
 409         # store release when st ready *and* all operands read (and no shadow)
 410         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 411                                self.shadown_i)
 412
 413         # request write of LD result.  waits until shadow is dropped.
 414         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 415                                   self.shadown_i)
 416
 417         # request write of EA result only in update mode
 418         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 419                                   self.shadown_i)
 420
 421         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 422         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 423         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 424                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 425                      (lod_l.qn | op_is_st))
 426         comb += self.done_o.eq(wr_reset)
 427
 428         ######################
 429         # Data/Address outputs
 430
 431         # put the LD-output register directly onto the output bus on a go_write
 432         with m.If(self.wr.go[0]):
 433             comb += self.data_o.eq(ldd_r)
 434
 435         # "update" mode, put address out on 2nd go-write
 436         with m.If(op_is_update & self.wr.go[1]):
 437             comb += self.addr_o.eq(addr_r)
 438
 439         ###########################
 440         # PortInterface connections
 441         pi = self.pi
 442
 443         # connect to LD/ST PortInterface.
 444         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 445         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 446         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 447         # address
 448         comb += pi.addr.data.eq(addr_r)           # EA from adder
 449         comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
 450         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 451         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 452         # ld - ld gets latched in via lod_l
 453         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 454         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 455         # store - data goes in based on go_st
 456         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 457         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 458
 459         return m
 460
 461     def __iter__(self):
 462         yield self.rd.go
 463         yield self.go_ad_i
 464         yield self.wr.go
 465         yield self.go_st_i
 466         yield self.issue_i
 467         yield self.shadown_i
 468         yield self.go_die_i
 469         yield from self.oper_i.ports()
 470         yield from self.src_i
 471         yield self.busy_o
 472         yield self.rd.rel
 473         yield self.adr_rel_o
 474         yield self.sto_rel_o
 475         yield self.wr.rel
 476         yield self.data_o
 477         yield self.addr_o
 478         yield self.load_mem_o
 479         yield self.stwd_mem_o
 480
 481     def ports(self):
 482         return list(self)
 483
 484
 485 def wait_for(sig, wait=True, test1st=False):
 486     v = (yield sig)
 487     print("wait for", sig, v, wait, test1st)
 488     if test1st and bool(v) == wait:
 489         return
 490     while True:
 491         yield
 492         v = (yield sig)
 493         #print("...wait for", sig, v)
 494         if bool(v) == wait:
 495             break
 496
 497
 498 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 499     print ("ST", src1, src2, src3, imm, imm_ok, update)
 500     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 501     yield dut.src1_i.eq(src1)
 502     yield dut.src2_i.eq(src2)
 503     yield dut.src3_i.eq(src3)
 504     yield dut.oper_i.imm_data.imm.eq(imm)
 505     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 506     yield dut.oper_i.update.eq(update)
 507     yield dut.issue_i.eq(1)
 508     yield
 509     yield dut.issue_i.eq(0)
 510     yield
 511     if imm_ok:
 512         yield dut.rd.go.eq(0b101)
 513     else:
 514         yield dut.rd.go.eq(0b111)
 515     yield from wait_for(dut.rd.rel)
 516     yield dut.rd.go.eq(0)
 517
 518     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 519     #yield from wait_for(dut.adr_rel_o)
 520     #yield dut.ad.go.eq(1)
 521     #yield
 522     #yield dut.ad.go.eq(0)
 523
 524     if update:
 525         yield from wait_for(dut.wr.rel[1])
 526         yield dut.wr.go.eq(0b10)
 527         yield
 528         addr = yield dut.addr_o
 529         print ("addr", addr)
 530         yield dut.wr.go.eq(0)
 531     else:
 532         addr = None
 533
 534     yield from wait_for(dut.sto_rel_o)
 535     yield dut.go_st_i.eq(1)
 536     yield
 537     yield dut.go_st_i.eq(0)
 538     yield from wait_for(dut.busy_o, False)
 539     #wait_for(dut.stwd_mem_o)
 540     yield
 541     return addr
 542
 543
 544 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
 545     print ("LD", src1, src2, imm, imm_ok, update)
 546     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 547     yield dut.src1_i.eq(src1)
 548     yield dut.src2_i.eq(src2)
 549     yield dut.oper_i.zero_a.eq(zero_a)
 550     yield dut.oper_i.imm_data.imm.eq(imm)
 551     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 552     yield dut.issue_i.eq(1)
 553     yield
 554     yield dut.issue_i.eq(0)
 555     yield
 556     rd = 0b00
 557     if not imm_ok:
 558         rd |= 0b10
 559     if not zero_a:
 560         rd |= 0b01
 561
 562     if rd:
 563         yield dut.rd.go.eq(rd)
 564         yield from wait_for(dut.rd.rel)
 565         yield dut.rd.go.eq(0)
 566
 567     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 568     #yield dut.ad.go.eq(1)
 569     #yield
 570     #yield dut.ad.go.eq(0)
 571
 572     if update:
 573         yield from wait_for(dut.wr.rel[1])
 574         yield dut.wr.go.eq(0b10)
 575         yield
 576         addr = yield dut.addr_o
 577         print ("addr", addr)
 578         yield dut.wr.go.eq(0)
 579     else:
 580         addr = None
 581
 582     yield from wait_for(dut.wr.rel[0], test1st=True)
 583     yield dut.wr.go.eq(1)
 584     yield
 585     data = yield dut.data_o
 586     print (data)
 587     yield dut.wr.go.eq(0)
 588     yield from wait_for(dut.busy_o)
 589     yield
 590     # wait_for(dut.stwd_mem_o)
 591     return data, addr
 592
 593
 594 def scoreboard_sim(dut):
 595
 596     ###################
 597     # immediate version
 598
 599     # two STs (different addresses)
 600     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 601     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 602     yield
 603     # two LDs (deliberately LD from the 1st address then 2nd)
 604     data, addr = yield from load(dut, 4, 0, 2)
 605     assert data == 0x0003, "returned %x" % data
 606     data, addr  = yield from load(dut, 2, 0, 2)
 607     assert data == 0x0009, "returned %x" % data
 608     yield
 609
 610     # indexed version
 611     yield from store(dut, 4, 5, 3, 0, imm_ok=False)
 612     data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
 613     assert data == 0x0003, "returned %x" % data
 614
 615     # update-immediate version
 616     addr = yield from store(dut, 4, 6, 3, 2, update=True)
 617     assert addr == 0x0006, "returned %x" % addr
 618
 619     # update-indexed version
 620     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
 621     assert data == 0x0003, "returned %x" % data
 622     assert addr == 0x0009, "returned %x" % addr
 623
 624     # immediate *and* zero version
 625     data, addr  = yield from load(dut, 4, 5, 9, imm_ok=True, zero_a=True)
 626     assert data == 0x0003, "returned %x" % data
 627
 628
 629 class TestLDSTCompUnit(LDSTCompUnit):
 630
 631     def __init__(self, rwid):
 632         from soc.experiment.l0_cache import TstL0CacheBuffer
 633         self.l0 = l0 = TstL0CacheBuffer()
 634         pi = l0.l0.dports[0].pi
 635         LDSTCompUnit.__init__(self, pi, rwid, 4)
 636
 637     def elaborate(self, platform):
 638         m = LDSTCompUnit.elaborate(self, platform)
 639         m.submodules.l0 = self.l0
 640         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 641         return m
 642
 643
 644 def test_scoreboard():
 645
 646     dut = TestLDSTCompUnit(16)
 647     vl = rtlil.convert(dut, ports=dut.ports())
 648     with open("test_ldst_comp.il", "w") as f:
 649         f.write(vl)
 650
 651     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 652
 653
 654 if __name__ == '__main__':
 655     test_scoreboard()