src/soc/experiment/compldst_multi.py

   1 """ LOAD / STORE Computation Unit.
   2
   3     This module covers POWER9-compliant Load and Store operations,
   4     with selection on each between immediate and indexed mode as
   5     options for the calculation of the Effective Address (EA),
   6     and also "update" mode which optionally stores that EA into
   7     an additional register.
   8
   9     ----
  10     Note: it took 15 attempts over several weeks to redraw the diagram
  11     needed to capture this FSM properly.  To understand it fully, please
  12     take the time to review the links, video, and diagram.
  13     ----
  14
  15     Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16     compute the "Effective Address", and, when ready the operand (src3_i)
  17     is stored in the computed address (passed through to the PortInterface)
  18
  19     Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20     and (as long as there was no exception) the data comes out (at any
  21     time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23     Both LD and ST may request that the address be computed from summing
  24     operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25     the immediate (from the opcode).
  26
  27     Both LD and ST may also request "update" mode (op_is_update) which
  28     activates the use of Go_Write[1] to control storage of the EA into
  29     a *second* operand in the register file.
  30
  31     Thus this module has *TWO* write-requests to the register file and
  32     *THREE* read-requests to the register file (not all at the same time!)
  33     The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45     It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46     is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47     the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59     Full diagram:
  60     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  61
  62     Links including to walk-through videos:
  63     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  64
  65     Related Bugreports:
  66     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  67
  68     Terminology:
  69
  70     * EA - Effective Address
  71     * LD - Load
  72     * ST - Store
  73 """
  74
  75 from nmigen.compat.sim import run_simulation
  76 from nmigen.cli import verilog, rtlil
  77 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  78 from nmigen.hdl.rec import Record, Layout
  79
  80 from nmutil.latch import SRLatch, latchregister
  81
  82 from soc.experiment.compalu_multi import go_record
  83 from soc.experiment.l0_cache import PortInterface
  84 from soc.experiment.testmem import TestMemory
  85 from soc.decoder.power_enums import InternalOp
  86
  87 from soc.decoder.power_enums import InternalOp, Function
  88
  89
  90 class CompLDSTOpSubset(Record):
  91     """CompLDSTOpSubset
  92
  93     a copy of the relevant subset information from Decode2Execute1Type
  94     needed for LD/ST operations.  use with eq_from_execute1 (below) to
  95     grab subsets.
  96     """
  97     def __init__(self, name=None):
  98         layout = (('insn_type', InternalOp),
  99                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
 100                   ('is_32bit', 1),
 101                   ('is_signed', 1),
 102                   ('data_len', 4), # TODO: should be in separate CompLDSTSubset
 103                   ('byte_reverse', 1),
 104                   ('sign_extend', 1),
 105                   ('update', 1))
 106
 107         Record.__init__(self, Layout(layout), name=name)
 108
 109         # grrr.  Record does not have kwargs
 110         self.insn_type.reset_less = True
 111         self.is_32bit.reset_less = True
 112         self.is_signed.reset_less = True
 113         self.data_len.reset_less = True
 114         self.byte_reverse.reset_less = True
 115         self.sign_extend.reset_less = True
 116         self.update.reset_less = True
 117
 118     def eq_from_execute1(self, other):
 119         """ use this to copy in from Decode2Execute1Type
 120         """
 121         res = []
 122         for fname, sig in self.fields.items():
 123             eqfrom = other.fields[fname]
 124             res.append(sig.eq(eqfrom))
 125         return res
 126
 127     def ports(self):
 128         return [self.insn_type,
 129                 self.is_32bit,
 130                 self.is_signed,
 131                 self.data_len,
 132                 self.byte_reverse,
 133                 self.sign_extend,
 134                 self.update,
 135         ]
 136
 137
 138 class LDSTCompUnit(Elaboratable):
 139     """LOAD / STORE Computation Unit
 140
 141     Inputs
 142     ------
 143
 144     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 145     * :rwid:   register width
 146     * :awid:   address width
 147
 148     Data inputs
 149     -----------
 150     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 151
 152     Data (outputs)
 153     --------------
 154     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 155     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 156     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 157
 158     TODO: make addr_exc_o a data-type rather than a single-bit signal
 159           (see bug #302)
 160
 161     Control Signals (In)
 162     --------------------
 163
 164     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 165     * :issue_i:    LD/ST is being "issued".
 166     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 167     * :go_rd_i:    read is being actioned (latches in src regs)
 168     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 169     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 170     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 171     * :go_die_i:   resets the unit back to "wait for issue"
 172
 173     Control Signals (Out)
 174     ---------------------
 175
 176     * :busy_o:      function unit is busy
 177     * :rd_rel_o:    request src1/src2
 178     * :adr_rel_o:   request address (from mem)
 179     * :sto_rel_o:   request store (to mem)
 180     * :req_rel_o:   request write (result)
 181     * :load_mem_o:  activate memory LOAD
 182     * :stwd_mem_o:  activate memory STORE
 183
 184     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 185     in a single cycle and the CompUnit set back to doing another op.
 186     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 187     depending on whether the operation is a ST or LD.
 188     """
 189
 190     def __init__(self, pi, rwid=64, awid=48, debugtest=False):
 191         self.rwid = rwid
 192         self.awid = awid
 193         self.pi = pi
 194         self.debugtest = debugtest
 195
 196         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 197         self.n_src = n_src = 3   # RA, RB, RT/RS
 198         self.n_dst = n_dst = 2 # RA, RT/RS
 199
 200         # set up array of src and dest signals
 201         src = []
 202         for i in range(n_src):
 203             j = i + 1 # name numbering to match src1/src2
 204             src.append(Signal(rwid, name="src%d_i" % j, reset_less=True))
 205
 206         dst = []
 207         for i in range(n_dst):
 208             j = i + 1 # name numbering to match dest1/2...
 209             dst.append(Signal(rwid, name="dest%d_i" % j, reset_less=True))
 210
 211         # control (dual in/out)
 212         self.rd = go_record(n_src, name="rd") # read in, req out
 213         self.wr = go_record(n_dst, name="wr") # write in, req out
 214         self.ad = go_record(1, name="ad") # address go in, req out
 215         self.st = go_record(1, name="st") # store go in, req out
 216
 217         self.go_rd_i = self.rd.go # temporary naming
 218         self.go_wr_i = self.wr.go # temporary naming
 219         self.rd_rel_o = self.rd.rel # temporary naming
 220         self.req_rel_o = self.wr.rel # temporary naming
 221
 222         self.go_ad_i = self.ad.go # temp naming: go address in
 223         self.go_st_i = self.st.go  # temp naming: go store in
 224
 225         # control inputs
 226         self.issue_i = Signal(reset_less=True)  # fn issue in
 227         self.shadown_i = Signal(reset=1)  # shadow function, defaults to ON
 228         self.go_die_i = Signal()  # go die (reset)
 229
 230         # operation / data input
 231         self.oper_i = CompLDSTOpSubset() # operand
 232         self.src_i = Array(src)
 233         self.src1_i = src[0] # oper1 in: RA
 234         self.src2_i = src[1] # oper2 in: RB
 235         self.src3_i = src[2] # oper2 in: RC (RS)
 236
 237         # outputs
 238         self.busy_o = Signal(reset_less=True)       # fn busy out
 239         self.done_o = Signal(reset_less=True)  # final release signal
 240         # TODO (see bug #302)
 241         self.addr_exc_o = Signal(reset_less=True)   # address exception
 242         self.dest = Array(dst)
 243         self.data_o = dst[0]  # Dest1 out: RT
 244         self.addr_o = dst[1]  # Address out (LD or ST) - Update => RA
 245
 246         self.adr_rel_o = self.ad.rel  # request address (from mem)
 247         self.sto_rel_o = self.st.rel  # request store (to mem)
 248
 249         self.ld_o = Signal(reset_less=True)  # operation is a LD
 250         self.st_o = Signal(reset_less=True)  # operation is a ST
 251
 252         # hmm... are these necessary?
 253         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 254         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 255
 256     def elaborate(self, platform):
 257         m = Module()
 258
 259         # temp/convenience
 260         comb = m.d.comb
 261         sync = m.d.sync
 262         issue_i = self.issue_i
 263
 264         #####################
 265         # latches for the FSM.
 266         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 267         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 268         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 269         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 270         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 271         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 272         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 273         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 274         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 275
 276         ####################
 277         # signals
 278
 279         # opcode decode
 280         op_is_ld = Signal(reset_less=True)
 281         op_is_st = Signal(reset_less=True)
 282
 283         # ALU/LD data output control
 284         alu_valid = Signal(reset_less=True) # ALU operands are valid
 285         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 286         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 287         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 288         wr_any = Signal(reset_less=True)    # any write (incl. store)
 289         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 290         wr_reset = Signal(reset_less=True)  # final reset condition
 291
 292         # LD and ALU out
 293         alu_o = Signal(self.rwid, reset_less=True)
 294         ld_o = Signal(self.rwid, reset_less=True)
 295
 296         # select immediate or src2 reg to add
 297         src2_or_imm = Signal(self.rwid, reset_less=True)
 298         src_sel = Signal(reset_less=True)
 299
 300         ##############################
 301         # reset conditions for latches
 302
 303         # temporaries (also convenient when debugging)
 304         reset_o = Signal(reset_less=True)             # reset opcode
 305         reset_w = Signal(reset_less=True)             # reset write
 306         reset_u = Signal(reset_less=True)             # reset update
 307         reset_a = Signal(reset_less=True)             # reset adr latch
 308         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 309         reset_r = Signal(self.n_src, reset_less=True) # reset src
 310         reset_s = Signal(reset_less=True)             # reset store
 311
 312         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 313         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 314         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 315         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 316         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 317         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 318         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 319
 320         ##########################
 321         # FSM implemented through sequence of latches.  approximately this:
 322         # - opc_l       : opcode
 323         #    - src_l[0] : operands
 324         #    - src_l[1]
 325         #       - alu_l : looks after add of src1/2/imm (EA)
 326         #       - adr_l : waits for add (EA)
 327         #       - upd_l : waits for adr and Regfile (port 2)
 328         #    - src_l[2] : ST
 329         # - lod_l       : waits for adr (EA) and for LD Data
 330         # - wri_l       : waits for LD Data and Regfile (port 1)
 331         # - st_l        : waits for alu and operand2
 332         # - rst_l       : waits for all FSM paths to converge.
 333         # NOTE: use sync to stop combinatorial loops.
 334
 335         # opcode latch - inverted so that busy resets to 0
 336         # note this MUST be sync so as to avoid a combinatorial loop
 337         # between busy_o and issue_i on the reset latch (rst_l)
 338         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 339         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 340
 341         # src operand latch
 342         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 343         sync += src_l.r.eq(reset_r)
 344
 345         # alu latch
 346         comb += alu_l.s.eq(alu_ok)
 347         comb += alu_l.r.eq(reset_i)
 348
 349         # addr latch
 350         comb += adr_l.s.eq(reset_a)
 351         comb += adr_l.r.eq(alu_ok)
 352
 353         # ld latch
 354         comb += lod_l.s.eq(reset_i)
 355         comb += lod_l.r.eq(ld_ok)
 356
 357         # dest operand latch
 358         sync += wri_l.s.eq(issue_i)
 359         sync += wri_l.r.eq(reset_w)
 360
 361         # update-mode operand latch (EA written to reg 2)
 362         sync += upd_l.s.eq(alu_ok)
 363         sync += upd_l.r.eq(reset_u)
 364
 365         # store latch
 366         sync += sto_l.s.eq(addr_ok & op_is_st)
 367         sync += sto_l.r.eq(reset_s)
 368
 369         # reset latch
 370         comb += rst_l.s.eq(addr_ok) # start when address is ready
 371         comb += rst_l.r.eq(issue_i)
 372
 373         # create a latch/register for the operand
 374         oper_r = CompLDSTOpSubset()  # Dest register
 375         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_r")
 376
 377         # and for LD
 378         ldd_r = Signal(self.rwid, reset_less=True)  # Dest register
 379         latchregister(m, ld_o, ldd_r, lod_l.q, "ldo_r")
 380
 381         # and for each input from the incoming src operands
 382         srl = []
 383         for i in range(self.n_src):
 384             name = "src_r%d" % i
 385             src_r = Signal(self.rwid, name=name, reset_less=True)
 386             latchregister(m, self.src_i[i], src_r, src_l.q[i], name)
 387             srl.append(src_r)
 388
 389         # and one for the output from the ADD (for the EA)
 390         addr_r = Signal(self.rwid, reset_less=True)  # Effective Address Latch
 391         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 392
 393         # select either immediate or src2 if opcode says so
 394         op_is_imm = oper_r.imm_data.imm_ok
 395         src2_or_imm = Signal(self.rwid, reset_less=True)
 396         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[0]))
 397
 398         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 399         sync += alu_o.eq(src_r[0] + src2_or_imm) # actual EA
 400         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 401
 402         # outputs: busy and release signals
 403         busy_o = self.busy_o
 404         comb += self.busy_o.eq(opc_l.q)  # busy out
 405         comb += self.rd.rel.eq(src_l.q & busy_o)  # src1/src2 req rel
 406         comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i & op_is_st)
 407
 408         # decode bits of operand (latched)
 409         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 410         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 411         op_is_update = oper_r.update                                 # UPDATE
 412         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 413         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 414         comb += self.ld_o.eq(op_is_ld)
 415         comb += self.st_o.eq(op_is_st)
 416
 417         ############################
 418         # Control Signal calculation
 419
 420         # 1st operand read-request is simple: always need it
 421         comb += self.rd.rel[0].eq(src_l.q[0] & busy_o)
 422
 423         # 2nd operand only needed when immediate is not active
 424         comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
 425
 426         # alu input valid when 1st and 2nd ops done (or imm not active)
 427         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 428
 429         # 3rd operand only needed when operation is a store
 430         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 431
 432         # all reads done when alu is valid and 3rd operand needed
 433         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 434
 435         # address release only if addr ready, but Port must be idle
 436         comb += self.adr_rel_o.eq(adr_l.q & busy_o & ~self.pi.busy_o)
 437
 438         # store release when st ready *and* all operands read (and no shadow)
 439         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 440                                self.shadown_i)
 441
 442         # request write of LD result.  waits until shadow is dropped.
 443         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 444                                   self.shadown_i)
 445
 446         # request write of EA result only in update mode
 447         comb += self.wr.rel[0].eq(upd_l.q & busy_o & op_is_update &
 448                                   self.shadown_i)
 449
 450         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 451         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 452         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i & wr_any &
 453                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) & lod_l.qn)
 454         comb += self.done_o.eq(wr_reset)
 455
 456         ######################
 457         # Data/Address outputs
 458
 459         # put the LD-output register directly onto the output bus on a go_write
 460         with m.If(self.wr.go[0]):
 461             comb += self.data_o.eq(ldd_r)
 462
 463         # "update" mode, put address out on 2nd go-write
 464         with m.If(op_is_update & self.wr.go[1]):
 465             comb += self.addr_o.eq(addr_r)
 466
 467         ###########################
 468         # PortInterface connections
 469         pi = self.pi
 470
 471         # connect to LD/ST PortInterface.
 472         comb += pi.is_ld_i.eq(op_is_ld)  # decoded-LD
 473         comb += pi.is_st_i.eq(op_is_st)  # decoded-ST
 474         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 475         # address
 476         comb += pi.addr.data.eq(addr_r)           # EA from adder
 477         comb += pi.addr.ok.eq(self.ad.go)         # "go do address stuff"
 478         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 479         comb += addr_ok.eq(self.pi.addr_ok_o)     # no exc, address fine
 480         # ld - ld gets latched in via lod_l
 481         comb += ld_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 482         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 483         # store - data goes in based on go_st
 484         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 485         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 486
 487         return m
 488
 489     def __iter__(self):
 490         yield self.rd.go
 491         yield self.go_ad_i
 492         yield self.wr.go
 493         yield self.go_st_i
 494         yield self.issue_i
 495         yield self.shadown_i
 496         yield self.go_die_i
 497         yield from self.oper_i.ports()
 498         yield from self.src_i
 499         yield self.busy_o
 500         yield self.rd.rel
 501         yield self.adr_rel_o
 502         yield self.sto_rel_o
 503         yield self.wr.rel
 504         yield self.data_o
 505         yield self.addr_o
 506         yield self.load_mem_o
 507         yield self.stwd_mem_o
 508
 509     def ports(self):
 510         return list(self)
 511
 512
 513 def wait_for(sig):
 514     v = (yield sig)
 515     print("wait for", sig, v)
 516     while True:
 517         yield
 518         v = (yield sig)
 519         print(v)
 520         if v:
 521             break
 522
 523
 524 def store(dut, src1, src2, imm, imm_ok=True):
 525     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 526     yield dut.src1_i.eq(src1)
 527     yield dut.src2_i.eq(src2)
 528     yield dut.oper_i.imm_data.imm.eq(imm)
 529     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 530     yield dut.issue_i.eq(1)
 531     yield
 532     yield dut.issue_i.eq(0)
 533     yield
 534     yield dut.rd.go.eq(0b11)
 535     yield from wait_for(dut.rd.rel)
 536     yield dut.rd.go.eq(0)
 537     yield from wait_for(dut.adr_rel_o)
 538     yield dut.go_st_i.eq(1)
 539     yield from wait_for(dut.sto_rel_o)
 540     wait_for(dut.stwd_mem_o)
 541     yield dut.go_st_i.eq(0)
 542     yield
 543
 544
 545 def load(dut, src1, src2, imm, imm_ok=True):
 546     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 547     yield dut.src1_i.eq(src1)
 548     yield dut.src2_i.eq(src2)
 549     yield dut.oper_i.imm_data.imm.eq(imm)
 550     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 551     yield dut.issue_i.eq(1)
 552     yield
 553     yield dut.issue_i.eq(0)
 554     yield
 555     yield dut.rd.go.eq(0b11)
 556     yield from wait_for(dut.rd.rel)
 557     yield dut.rd.go.eq(0)
 558     yield from wait_for(dut.adr_rel_o)
 559     yield dut.go_ad_i.eq(1)
 560     yield from wait_for(dut.busy_o)
 561     yield
 562     data = (yield dut.data_o)
 563     yield dut.go_ad_i.eq(0)
 564     # wait_for(dut.stwd_mem_o)
 565     return data
 566
 567
 568 def add(dut, src1, src2, imm, imm_ok=False):
 569     yield dut.oper_i.insn_type.eq(InternalOp.OP_ADD)
 570     yield dut.src1_i.eq(src1)
 571     yield dut.src2_i.eq(src2)
 572     yield dut.oper_i.imm_data.imm.eq(imm)
 573     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 574     yield dut.issue_i.eq(1)
 575     yield
 576     yield dut.issue_i.eq(0)
 577     yield
 578     yield dut.rd.go.eq(1)
 579     yield from wait_for(dut.rd.rel)
 580     yield dut.rd.go.eq(0)
 581     yield from wait_for(dut.wr.rel)
 582     yield dut.wr.go.eq(1)
 583     yield from wait_for(dut.busy_o)
 584     yield
 585     data = (yield dut.data_o)
 586     yield dut.wr.go.eq(0)
 587     yield
 588     # wait_for(dut.stwd_mem_o)
 589     return data
 590
 591
 592 def scoreboard_sim(dut):
 593     # two STs (different addresses)
 594     yield from store(dut, 4, 3, 2)
 595     yield from store(dut, 2, 9, 2)
 596     yield
 597     # two LDs (deliberately LD from the 1st address then 2nd)
 598     data = yield from load(dut, 4, 0, 2)
 599     assert data == 0x0003
 600     data = yield from load(dut, 2, 0, 2)
 601     assert data == 0x0009
 602     yield
 603
 604     # now do an add
 605     data = yield from add(dut, 4, 3, 0xfeed)
 606     assert data == 0x7
 607
 608     # and an add-immediate
 609     data = yield from add(dut, 4, 0xdeef, 2, imm_ok=True)
 610     assert data == 0x6
 611
 612
 613 class TestLDSTCompUnit(LDSTCompUnit):
 614
 615     def __init__(self, rwid):
 616         from soc.experiment.l0_cache import TstL0CacheBuffer
 617         self.l0 = l0 = TstL0CacheBuffer()
 618         pi = l0.l0.dports[0].pi
 619         LDSTCompUnit.__init__(self, pi, rwid, 4)
 620
 621     def elaborate(self, platform):
 622         m = LDSTCompUnit.elaborate(self, platform)
 623         m.submodules.l0 = self.l0
 624         return m
 625
 626
 627 def test_scoreboard():
 628
 629     dut = TestLDSTCompUnit(16)
 630     vl = rtlil.convert(dut, ports=dut.ports())
 631     with open("test_ldst_comp.il", "w") as f:
 632         f.write(vl)
 633
 634     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 635
 636
 637 if __name__ == '__main__':
 638     test_scoreboard()