src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 Both LD and ST may request that the address be computed from summing
  24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25 the immediate (from the opcode).
  26
  27 Both LD and ST may also request "update" mode (op_is_update) which
  28 activates the use of Go_Write[1] to control storage of the EA into
  29 a *second* operand in the register file.
  30
  31 Thus this module has *TWO* write-requests to the register file and
  32 *THREE* read-requests to the register file (not all at the same time!)
  33 The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47 the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59 Full diagram:
  60
  61     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  62
  63 Links including to walk-through videos:
  64
  65     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  66     * http://libre-soc.org/openpower/isa/fixedload
  67     * http://libre-soc.org/openpower/isa/fixedstore
  68
  69 Related Bugreports:
  70
  71     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  72     * https://bugs.libre-soc.org/show_bug.cgi?id=216
  73
  74 Terminology:
  75
  76     * EA - Effective Address
  77     * LD - Load
  78     * ST - Store
  79 """
  80
  81 from nmigen.compat.sim import run_simulation
  82 from nmigen.cli import verilog, rtlil
  83 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  84 from nmigen.hdl.rec import Record, Layout
  85
  86 from nmutil.latch import SRLatch, latchregister
  87
  88 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  89 from soc.experiment.l0_cache import PortInterface
  90 from soc.experiment.testmem import TestMemory
  91 from soc.fu.regspec import RegSpecAPI
  92
  93 from soc.decoder.power_enums import InternalOp, Function
  94 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  95 from soc.decoder.power_decoder2 import Data
  96
  97
  98 class LDSTCompUnitRecord(CompUnitRecord):
  99     def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
 100         CompUnitRecord.__init__(self, opsubset, rwid,
 101                                 n_src=3, n_dst=2, name=name)
 102
 103         self.ad = go_record(1, name="ad") # address go in, req out
 104         self.st = go_record(1, name="st") # store go in, req out
 105
 106         self.addr_exc_o = Signal(reset_less=True)   # address exception
 107
 108         self.ld_o = Signal(reset_less=True)  # operation is a LD
 109         self.st_o = Signal(reset_less=True)  # operation is a ST
 110
 111         # hmm... are these necessary?
 112         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 113         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 114
 115
 116 class LDSTCompUnit(RegSpecAPI, Elaboratable):
 117     """LOAD / STORE Computation Unit
 118
 119     Inputs
 120     ------
 121
 122     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 123     * :rwid:   register width
 124     * :awid:   address width
 125
 126     Data inputs
 127     -----------
 128     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 129
 130     Data (outputs)
 131     --------------
 132     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 133     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 134     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 135
 136     TODO: make addr_exc_o a data-type rather than a single-bit signal
 137           (see bug #302)
 138
 139     Control Signals (In)
 140     --------------------
 141
 142     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 143     * :issue_i:    LD/ST is being "issued".
 144     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 145     * :go_rd_i:    read is being actioned (latches in src regs)
 146     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 147     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 148     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 149     * :go_die_i:   resets the unit back to "wait for issue"
 150
 151     Control Signals (Out)
 152     ---------------------
 153
 154     * :busy_o:      function unit is busy
 155     * :rd_rel_o:    request src1/src2
 156     * :adr_rel_o:   request address (from mem)
 157     * :sto_rel_o:   request store (to mem)
 158     * :req_rel_o:   request write (result)
 159     * :load_mem_o:  activate memory LOAD
 160     * :stwd_mem_o:  activate memory STORE
 161
 162     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 163     in a single cycle and the CompUnit set back to doing another op.
 164     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 165     depending on whether the operation is a ST or LD.
 166     """
 167
 168     def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
 169                       debugtest=False):
 170         super().__init__(rwid)
 171         self.awid = awid
 172         self.pi = pi
 173         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset)
 174         self.debugtest = debugtest
 175
 176         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 177         self.n_src = n_src = 3   # RA, RB, RT/RS
 178         self.n_dst = n_dst = 2 # RA, RT/RS
 179
 180         # set up array of src and dest signals
 181         for i in range(n_src):
 182             j = i + 1 # name numbering to match src1/src2
 183             name = "src%d_i" % j
 184             setattr(self, name, getattr(cu, name))
 185
 186         dst = []
 187         for i in range(n_dst):
 188             j = i + 1 # name numbering to match dest1/2...
 189             name = "dest%d_o" % j
 190             setattr(self, name, getattr(cu, name))
 191
 192         # convenience names
 193         self.rd = cu.rd
 194         self.wr = cu.wr
 195         self.rdmaskn = cu.rdmaskn
 196         self.wrmask = cu.wrmask
 197         self.ad = cu.ad
 198         self.st = cu.st
 199         self.dest = cu._dest
 200
 201         # HACK: get data width from dest[0].  this is used across the board
 202         # (it really shouldn't be)
 203         self.data_wid = self.dest[0].shape()
 204
 205         self.go_rd_i = self.rd.go # temporary naming
 206         self.go_wr_i = self.wr.go # temporary naming
 207         self.go_ad_i = self.ad.go # temp naming: go address in
 208         self.go_st_i = self.st.go  # temp naming: go store in
 209
 210         self.rd_rel_o = self.rd.rel # temporary naming
 211         self.req_rel_o = self.wr.rel # temporary naming
 212         self.adr_rel_o = self.ad.rel  # request address (from mem)
 213         self.sto_rel_o = self.st.rel  # request store (to mem)
 214
 215         self.issue_i = cu.issue_i
 216         self.shadown_i = cu.shadown_i
 217         self.go_die_i = cu.go_die_i
 218
 219         self.oper_i = cu.oper_i
 220         self.src_i = cu._src_i
 221
 222         self.data_o = Data(self.data_wid, name="o")  # Dest1 out: RT
 223         self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
 224         self.addr_exc_o = cu.addr_exc_o
 225         self.done_o = cu.done_o
 226         self.busy_o = cu.busy_o
 227
 228         self.ld_o = cu.ld_o
 229         self.st_o = cu.st_o
 230
 231         self.load_mem_o = cu.load_mem_o
 232         self.stwd_mem_o = cu.stwd_mem_o
 233
 234     def elaborate(self, platform):
 235         m = Module()
 236
 237         # temp/convenience
 238         comb = m.d.comb
 239         sync = m.d.sync
 240         issue_i = self.issue_i
 241
 242         #####################
 243         # latches for the FSM.
 244         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 245         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 246         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 247         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 248         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 249         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 250         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 251         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 252         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 253
 254         ####################
 255         # signals
 256
 257         # opcode decode
 258         op_is_ld = Signal(reset_less=True)
 259         op_is_st = Signal(reset_less=True)
 260
 261         # ALU/LD data output control
 262         alu_valid = Signal(reset_less=True) # ALU operands are valid
 263         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 264         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 265         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 266         wr_any = Signal(reset_less=True)    # any write (incl. store)
 267         rda_any = Signal(reset_less=True)   # any read for address ops
 268         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 269         wr_reset = Signal(reset_less=True)  # final reset condition
 270
 271         # LD and ALU out
 272         alu_o = Signal(self.data_wid, reset_less=True)
 273         ldd_o = Signal(self.data_wid, reset_less=True)
 274
 275         ##############################
 276         # reset conditions for latches
 277
 278         # temporaries (also convenient when debugging)
 279         reset_o = Signal(reset_less=True)             # reset opcode
 280         reset_w = Signal(reset_less=True)             # reset write
 281         reset_u = Signal(reset_less=True)             # reset update
 282         reset_a = Signal(reset_less=True)             # reset adr latch
 283         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 284         reset_r = Signal(self.n_src, reset_less=True) # reset src
 285         reset_s = Signal(reset_less=True)             # reset store
 286
 287         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 288         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 289         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 290         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 291         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 292         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 293         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 294
 295         ##########################
 296         # FSM implemented through sequence of latches.  approximately this:
 297         # - opc_l       : opcode
 298         #    - src_l[0] : operands
 299         #    - src_l[1]
 300         #       - alu_l : looks after add of src1/2/imm (EA)
 301         #       - adr_l : waits for add (EA)
 302         #       - upd_l : waits for adr and Regfile (port 2)
 303         #    - src_l[2] : ST
 304         # - lod_l       : waits for adr (EA) and for LD Data
 305         # - wri_l       : waits for LD Data and Regfile (port 1)
 306         # - st_l        : waits for alu and operand2
 307         # - rst_l       : waits for all FSM paths to converge.
 308         # NOTE: use sync to stop combinatorial loops.
 309
 310         # opcode latch - inverted so that busy resets to 0
 311         # note this MUST be sync so as to avoid a combinatorial loop
 312         # between busy_o and issue_i on the reset latch (rst_l)
 313         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 314         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 315
 316         # src operand latch
 317         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 318         sync += src_l.r.eq(reset_r)
 319
 320         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 321         comb += alu_l.s.eq(reset_i)
 322         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 323
 324         # addr latch
 325         comb += adr_l.s.eq(reset_i)
 326         sync += adr_l.r.eq(reset_a)
 327
 328         # ld latch
 329         comb += lod_l.s.eq(reset_i)
 330         comb += lod_l.r.eq(ld_ok)
 331
 332         # dest operand latch
 333         comb += wri_l.s.eq(issue_i)
 334         sync += wri_l.r.eq(reset_w)
 335
 336         # update-mode operand latch (EA written to reg 2)
 337         sync += upd_l.s.eq(reset_i)
 338         sync += upd_l.r.eq(reset_u)
 339
 340         # store latch
 341         comb += sto_l.s.eq(addr_ok & op_is_st)
 342         comb += sto_l.r.eq(reset_s)
 343
 344         # reset latch
 345         comb += rst_l.s.eq(addr_ok) # start when address is ready
 346         comb += rst_l.r.eq(issue_i)
 347
 348         # create a latch/register for the operand
 349         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 350         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 351
 352         # and for LD
 353         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
 354         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 355
 356         # and for each input from the incoming src operands
 357         srl = []
 358         for i in range(self.n_src):
 359             name = "src_r%d" % i
 360             src_r = Signal(self.data_wid, name=name, reset_less=True)
 361             latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
 362             srl.append(src_r)
 363
 364         # and one for the output from the ADD (for the EA)
 365         addr_r = Signal(self.data_wid, reset_less=True)  # Effective Address
 366         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 367
 368         # select either zero or src1 if opcode says so
 369         op_is_z = oper_r.zero_a
 370         src1_or_z = Signal(self.data_wid, reset_less=True)
 371         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 372
 373         # select either immediate or src2 if opcode says so
 374         op_is_imm = oper_r.imm_data.imm_ok
 375         src2_or_imm = Signal(self.data_wid, reset_less=True)
 376         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 377
 378         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 379         sync += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
 380         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 381
 382         # decode bits of operand (latched)
 383         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 384         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 385         op_is_update = oper_r.update                                 # UPDATE
 386         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 387         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 388         comb += self.ld_o.eq(op_is_ld)
 389         comb += self.st_o.eq(op_is_st)
 390
 391         ############################
 392         # Control Signal calculation
 393
 394         # busy signal
 395         busy_o = self.busy_o
 396         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 397
 398         # 1st operand read-request only when zero not active
 399         # 2nd operand only needed when immediate is not active
 400         slg = Cat(op_is_z, op_is_imm)
 401         bro = Repl(self.busy_o, self.n_src)
 402         comb += self.rd.rel.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
 403
 404         # note when the address-related read "go" signals are active
 405         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 406
 407         # alu input valid when 1st and 2nd ops done (or imm not active)
 408         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 409
 410         # 3rd operand only needed when operation is a store
 411         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 412
 413         # all reads done when alu is valid and 3rd operand needed
 414         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 415
 416         # address release only if addr ready, but Port must be idle
 417         comb += self.adr_rel_o.eq(adr_l.q & busy_o)
 418
 419         # store release when st ready *and* all operands read (and no shadow)
 420         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 421                                self.shadown_i)
 422
 423         # request write of LD result.  waits until shadow is dropped.
 424         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 425                                   self.shadown_i)
 426
 427         # request write of EA result only in update mode
 428         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 429                                   self.shadown_i)
 430
 431         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 432         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 433         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 434                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 435                      (lod_l.qn | op_is_st))
 436         comb += self.done_o.eq(wr_reset)
 437
 438         ######################
 439         # Data/Address outputs
 440
 441         # put the LD-output register directly onto the output bus on a go_write
 442         comb += self.data_o.data.eq(self.dest[0])
 443         with m.If(self.wr.go[0]):
 444             comb += self.dest[0].eq(ldd_r)
 445
 446         # "update" mode, put address out on 2nd go-write
 447         comb += self.addr_o.data.eq(self.dest[1])
 448         with m.If(op_is_update & self.wr.go[1]):
 449             comb += self.dest[1].eq(addr_r)
 450
 451         # need to look like MultiCompUnit: put wrmask out.
 452         # XXX may need to make this enable only when write active
 453         comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
 454
 455         ###########################
 456         # PortInterface connections
 457         pi = self.pi
 458
 459         # connect to LD/ST PortInterface.
 460         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 461         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 462         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 463         # address
 464         comb += pi.addr.data.eq(addr_r)           # EA from adder
 465         comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
 466         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 467         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 468         # ld - ld gets latched in via lod_l
 469         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 470         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 471         # store - data goes in based on go_st
 472         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 473         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 474
 475         return m
 476
 477     def get_out(self, i):
 478         """make LDSTCompUnit look like RegSpecALUAPI"""
 479         if i == 0:
 480             return self.data_o
 481         if i == 1:
 482             return self.addr_o
 483         #return self.dest[i]
 484
 485     def __iter__(self):
 486         yield self.rd.go
 487         yield self.go_ad_i
 488         yield self.wr.go
 489         yield self.go_st_i
 490         yield self.issue_i
 491         yield self.shadown_i
 492         yield self.go_die_i
 493         yield from self.oper_i.ports()
 494         yield from self.src_i
 495         yield self.busy_o
 496         yield self.rd.rel
 497         yield self.adr_rel_o
 498         yield self.sto_rel_o
 499         yield self.wr.rel
 500         yield from self.data_o.ports()
 501         yield from self.addr_o.ports()
 502         yield self.load_mem_o
 503         yield self.stwd_mem_o
 504
 505     def ports(self):
 506         return list(self)
 507
 508
 509 def wait_for(sig, wait=True, test1st=False):
 510     v = (yield sig)
 511     print("wait for", sig, v, wait, test1st)
 512     if test1st and bool(v) == wait:
 513         return
 514     while True:
 515         yield
 516         v = (yield sig)
 517         #print("...wait for", sig, v)
 518         if bool(v) == wait:
 519             break
 520
 521
 522 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 523     print ("ST", src1, src2, src3, imm, imm_ok, update)
 524     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 525     yield dut.oper_i.data_len.eq(2) # half-word
 526     yield dut.src1_i.eq(src1)
 527     yield dut.src2_i.eq(src2)
 528     yield dut.src3_i.eq(src3)
 529     yield dut.oper_i.imm_data.imm.eq(imm)
 530     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 531     yield dut.oper_i.update.eq(update)
 532     yield dut.issue_i.eq(1)
 533     yield
 534     yield dut.issue_i.eq(0)
 535     yield
 536     if imm_ok:
 537         yield dut.rd.go.eq(0b101)
 538     else:
 539         yield dut.rd.go.eq(0b111)
 540     yield from wait_for(dut.rd.rel)
 541     yield dut.rd.go.eq(0)
 542
 543     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 544     #yield from wait_for(dut.adr_rel_o)
 545     #yield dut.ad.go.eq(1)
 546     #yield
 547     #yield dut.ad.go.eq(0)
 548
 549     if update:
 550         yield from wait_for(dut.wr.rel[1])
 551         yield dut.wr.go.eq(0b10)
 552         yield
 553         addr = yield dut.addr_o
 554         print ("addr", addr)
 555         yield dut.wr.go.eq(0)
 556     else:
 557         addr = None
 558
 559     yield from wait_for(dut.sto_rel_o)
 560     yield dut.go_st_i.eq(1)
 561     yield
 562     yield dut.go_st_i.eq(0)
 563     yield from wait_for(dut.busy_o, False)
 564     #wait_for(dut.stwd_mem_o)
 565     yield
 566     return addr
 567
 568
 569 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
 570     print ("LD", src1, src2, imm, imm_ok, update)
 571     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 572     yield dut.oper_i.data_len.eq(2) # half-word
 573     yield dut.src1_i.eq(src1)
 574     yield dut.src2_i.eq(src2)
 575     yield dut.oper_i.zero_a.eq(zero_a)
 576     yield dut.oper_i.imm_data.imm.eq(imm)
 577     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 578     yield dut.issue_i.eq(1)
 579     yield
 580     yield dut.issue_i.eq(0)
 581     yield
 582     rd = 0b00
 583     if not imm_ok:
 584         rd |= 0b10
 585     if not zero_a:
 586         rd |= 0b01
 587
 588     if rd:
 589         yield dut.rd.go.eq(rd)
 590         yield from wait_for(dut.rd.rel)
 591         yield dut.rd.go.eq(0)
 592
 593     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 594     #yield dut.ad.go.eq(1)
 595     #yield
 596     #yield dut.ad.go.eq(0)
 597
 598     if update:
 599         yield from wait_for(dut.wr.rel[1])
 600         yield dut.wr.go.eq(0b10)
 601         yield
 602         addr = yield dut.addr_o
 603         print ("addr", addr)
 604         yield dut.wr.go.eq(0)
 605     else:
 606         addr = None
 607
 608     yield from wait_for(dut.wr.rel[0], test1st=True)
 609     yield dut.wr.go.eq(1)
 610     yield
 611     data = yield dut.data_o
 612     print (data)
 613     yield dut.wr.go.eq(0)
 614     yield from wait_for(dut.busy_o)
 615     yield
 616     # wait_for(dut.stwd_mem_o)
 617     return data, addr
 618
 619
 620 def scoreboard_sim(dut):
 621
 622     ###################
 623     # immediate version
 624
 625     # two STs (different addresses)
 626     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 627     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 628     yield
 629     # two LDs (deliberately LD from the 1st address then 2nd)
 630     data, addr = yield from load(dut, 4, 0, 2)
 631     assert data == 0x0003, "returned %x" % data
 632     data, addr  = yield from load(dut, 2, 0, 2)
 633     assert data == 0x0009, "returned %x" % data
 634     yield
 635
 636     # indexed version
 637     yield from store(dut, 4, 5, 3, 0, imm_ok=False)
 638     data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
 639     assert data == 0x0003, "returned %x" % data
 640
 641     # update-immediate version
 642     addr = yield from store(dut, 4, 6, 3, 2, update=True)
 643     assert addr == 0x0006, "returned %x" % addr
 644
 645     # update-indexed version
 646     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
 647     assert data == 0x0003, "returned %x" % data
 648     assert addr == 0x0009, "returned %x" % addr
 649
 650     # immediate *and* zero version
 651     data, addr  = yield from load(dut, 4, 5, 9, imm_ok=True, zero_a=True)
 652     assert data == 0x0003, "returned %x" % data
 653
 654
 655 class TestLDSTCompUnit(LDSTCompUnit):
 656
 657     def __init__(self, rwid):
 658         from soc.experiment.l0_cache import TstL0CacheBuffer
 659         self.l0 = l0 = TstL0CacheBuffer()
 660         pi = l0.l0.dports[0].pi
 661         LDSTCompUnit.__init__(self, pi, rwid, 4)
 662
 663     def elaborate(self, platform):
 664         m = LDSTCompUnit.elaborate(self, platform)
 665         m.submodules.l0 = self.l0
 666         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 667         return m
 668
 669
 670 def test_scoreboard():
 671
 672     dut = TestLDSTCompUnit(16)
 673     vl = rtlil.convert(dut, ports=dut.ports())
 674     with open("test_ldst_comp.il", "w") as f:
 675         f.write(vl)
 676
 677     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 678
 679
 680 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 681
 682     def __init__(self):
 683         from soc.experiment.l0_cache import TstL0CacheBuffer
 684         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 685         regspec = LDSTPipeSpec.regspec
 686         self.l0 = l0 = TstL0CacheBuffer()
 687         pi = l0.l0.dports[0].pi
 688         LDSTCompUnit.__init__(self, pi, regspec, 4)
 689
 690     def elaborate(self, platform):
 691         m = LDSTCompUnit.elaborate(self, platform)
 692         m.submodules.l0 = self.l0
 693         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 694         return m
 695
 696
 697 def test_scoreboard_regspec():
 698
 699     dut = TestLDSTCompUnitRegSpec()
 700     vl = rtlil.convert(dut, ports=dut.ports())
 701     with open("test_ldst_comp.il", "w") as f:
 702         f.write(vl)
 703
 704     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_regspec.vcd')
 705
 706
 707 if __name__ == '__main__':
 708     test_scoreboard_regspec()
 709     test_scoreboard()