src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 Both LD and ST may request that the address be computed from summing
  24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25 the immediate (from the opcode).
  26
  27 Both LD and ST may also request "update" mode (op_is_update) which
  28 activates the use of Go_Write[1] to control storage of the EA into
  29 a *second* operand in the register file.
  30
  31 Thus this module has *TWO* write-requests to the register file and
  32 *THREE* read-requests to the register file (not all at the same time!)
  33 The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47 the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59 Full diagram:
  60
  61     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  62
  63 Links including to walk-through videos:
  64
  65     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  66     * http://libre-soc.org/openpower/isa/fixedload
  67     * http://libre-soc.org/openpower/isa/fixedstore
  68
  69 Related Bugreports:
  70
  71     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  72     * https://bugs.libre-soc.org/show_bug.cgi?id=216
  73
  74 Terminology:
  75
  76     * EA - Effective Address
  77     * LD - Load
  78     * ST - Store
  79 """
  80
  81 from nmigen.compat.sim import run_simulation
  82 from nmigen.cli import verilog, rtlil
  83 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  84 from nmigen.hdl.rec import Record, Layout
  85
  86 from nmutil.latch import SRLatch, latchregister
  87
  88 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  89 from soc.experiment.l0_cache import PortInterface
  90 from soc.fu.regspec import RegSpecAPI
  91
  92 from soc.decoder.power_enums import InternalOp, Function
  93 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  94 from soc.decoder.power_decoder2 import Data
  95
  96
  97 class LDSTCompUnitRecord(CompUnitRecord):
  98     def __init__(self, rwid, opsubset=CompLDSTOpSubset, name=None):
  99         CompUnitRecord.__init__(self, opsubset, rwid,
 100                                 n_src=3, n_dst=2, name=name)
 101
 102         self.ad = go_record(1, name="ad") # address go in, req out
 103         self.st = go_record(1, name="st") # store go in, req out
 104
 105         self.addr_exc_o = Signal(reset_less=True)   # address exception
 106
 107         self.ld_o = Signal(reset_less=True)  # operation is a LD
 108         self.st_o = Signal(reset_less=True)  # operation is a ST
 109
 110         # hmm... are these necessary?
 111         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 112         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 113
 114
 115 class LDSTCompUnit(RegSpecAPI, Elaboratable):
 116     """LOAD / STORE Computation Unit
 117
 118     Inputs
 119     ------
 120
 121     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 122     * :rwid:   register width
 123     * :awid:   address width
 124
 125     Data inputs
 126     -----------
 127     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 128
 129     Data (outputs)
 130     --------------
 131     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 132     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 133     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 134
 135     TODO: make addr_exc_o a data-type rather than a single-bit signal
 136           (see bug #302)
 137
 138     Control Signals (In)
 139     --------------------
 140
 141     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 142     * :issue_i:    LD/ST is being "issued".
 143     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 144     * :go_rd_i:    read is being actioned (latches in src regs)
 145     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 146     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 147     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 148     * :go_die_i:   resets the unit back to "wait for issue"
 149
 150     Control Signals (Out)
 151     ---------------------
 152
 153     * :busy_o:      function unit is busy
 154     * :rd_rel_o:    request src1/src2
 155     * :adr_rel_o:   request address (from mem)
 156     * :sto_rel_o:   request store (to mem)
 157     * :req_rel_o:   request write (result)
 158     * :load_mem_o:  activate memory LOAD
 159     * :stwd_mem_o:  activate memory STORE
 160
 161     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 162     in a single cycle and the CompUnit set back to doing another op.
 163     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 164     depending on whether the operation is a ST or LD.
 165     """
 166
 167     def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset,
 168                       debugtest=False):
 169         super().__init__(rwid)
 170         self.awid = awid
 171         self.pi = pi
 172         self.cu = cu = LDSTCompUnitRecord(rwid, opsubset)
 173         self.debugtest = debugtest
 174
 175         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 176         self.n_src = n_src = 3   # RA, RB, RT/RS
 177         self.n_dst = n_dst = 2 # RA, RT/RS
 178
 179         # set up array of src and dest signals
 180         for i in range(n_src):
 181             j = i + 1 # name numbering to match src1/src2
 182             name = "src%d_i" % j
 183             setattr(self, name, getattr(cu, name))
 184
 185         dst = []
 186         for i in range(n_dst):
 187             j = i + 1 # name numbering to match dest1/2...
 188             name = "dest%d_o" % j
 189             setattr(self, name, getattr(cu, name))
 190
 191         # convenience names
 192         self.rd = cu.rd
 193         self.wr = cu.wr
 194         self.rdmaskn = cu.rdmaskn
 195         self.wrmask = cu.wrmask
 196         self.ad = cu.ad
 197         self.st = cu.st
 198         self.dest = cu._dest
 199
 200         # HACK: get data width from dest[0].  this is used across the board
 201         # (it really shouldn't be)
 202         self.data_wid = self.dest[0].shape()
 203
 204         self.go_rd_i = self.rd.go # temporary naming
 205         self.go_wr_i = self.wr.go # temporary naming
 206         self.go_ad_i = self.ad.go # temp naming: go address in
 207         self.go_st_i = self.st.go  # temp naming: go store in
 208
 209         self.rd_rel_o = self.rd.rel # temporary naming
 210         self.req_rel_o = self.wr.rel # temporary naming
 211         self.adr_rel_o = self.ad.rel  # request address (from mem)
 212         self.sto_rel_o = self.st.rel  # request store (to mem)
 213
 214         self.issue_i = cu.issue_i
 215         self.shadown_i = cu.shadown_i
 216         self.go_die_i = cu.go_die_i
 217
 218         self.oper_i = cu.oper_i
 219         self.src_i = cu._src_i
 220
 221         self.data_o = Data(self.data_wid, name="o")  # Dest1 out: RT
 222         self.addr_o = Data(self.data_wid, name="ea") # Addr out: Update => RA
 223         self.addr_exc_o = cu.addr_exc_o
 224         self.done_o = cu.done_o
 225         self.busy_o = cu.busy_o
 226
 227         self.ld_o = cu.ld_o
 228         self.st_o = cu.st_o
 229
 230         self.load_mem_o = cu.load_mem_o
 231         self.stwd_mem_o = cu.stwd_mem_o
 232
 233     def elaborate(self, platform):
 234         m = Module()
 235
 236         # temp/convenience
 237         comb = m.d.comb
 238         sync = m.d.sync
 239         issue_i = self.issue_i
 240
 241         #####################
 242         # latches for the FSM.
 243         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 244         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 245         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 246         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 247         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 248         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 249         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 250         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 251         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 252
 253         ####################
 254         # signals
 255
 256         # opcode decode
 257         op_is_ld = Signal(reset_less=True)
 258         op_is_st = Signal(reset_less=True)
 259
 260         # ALU/LD data output control
 261         alu_valid = Signal(reset_less=True) # ALU operands are valid
 262         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 263         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 264         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 265         wr_any = Signal(reset_less=True)    # any write (incl. store)
 266         rda_any = Signal(reset_less=True)   # any read for address ops
 267         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 268         wr_reset = Signal(reset_less=True)  # final reset condition
 269
 270         # LD and ALU out
 271         alu_o = Signal(self.data_wid, reset_less=True)
 272         ldd_o = Signal(self.data_wid, reset_less=True)
 273
 274         ##############################
 275         # reset conditions for latches
 276
 277         # temporaries (also convenient when debugging)
 278         reset_o = Signal(reset_less=True)             # reset opcode
 279         reset_w = Signal(reset_less=True)             # reset write
 280         reset_u = Signal(reset_less=True)             # reset update
 281         reset_a = Signal(reset_less=True)             # reset adr latch
 282         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 283         reset_r = Signal(self.n_src, reset_less=True) # reset src
 284         reset_s = Signal(reset_less=True)             # reset store
 285
 286         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 287         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 288         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 289         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 290         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 291         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 292         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 293
 294         p_st_go = Signal(reset_less=True)
 295         sync += p_st_go.eq(self.st.go)
 296
 297         ##########################
 298         # FSM implemented through sequence of latches.  approximately this:
 299         # - opc_l       : opcode
 300         #    - src_l[0] : operands
 301         #    - src_l[1]
 302         #       - alu_l : looks after add of src1/2/imm (EA)
 303         #       - adr_l : waits for add (EA)
 304         #       - upd_l : waits for adr and Regfile (port 2)
 305         #    - src_l[2] : ST
 306         # - lod_l       : waits for adr (EA) and for LD Data
 307         # - wri_l       : waits for LD Data and Regfile (port 1)
 308         # - st_l        : waits for alu and operand2
 309         # - rst_l       : waits for all FSM paths to converge.
 310         # NOTE: use sync to stop combinatorial loops.
 311
 312         # opcode latch - inverted so that busy resets to 0
 313         # note this MUST be sync so as to avoid a combinatorial loop
 314         # between busy_o and issue_i on the reset latch (rst_l)
 315         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 316         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 317
 318         # src operand latch
 319         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 320         sync += src_l.r.eq(reset_r)
 321
 322         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 323         comb += alu_l.s.eq(reset_i)
 324         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 325
 326         # addr latch
 327         comb += adr_l.s.eq(reset_i)
 328         sync += adr_l.r.eq(reset_a)
 329
 330         # ld latch
 331         comb += lod_l.s.eq(reset_i)
 332         comb += lod_l.r.eq(ld_ok)
 333
 334         # dest operand latch
 335         comb += wri_l.s.eq(issue_i)
 336         sync += wri_l.r.eq(reset_w | Repl(self.done_o, self.n_dst))
 337
 338         # update-mode operand latch (EA written to reg 2)
 339         sync += upd_l.s.eq(reset_i)
 340         sync += upd_l.r.eq(reset_u)
 341
 342         # store latch
 343         comb += sto_l.s.eq(addr_ok & op_is_st)
 344         comb += sto_l.r.eq(reset_s | p_st_go)
 345
 346         # reset latch
 347         comb += rst_l.s.eq(addr_ok) # start when address is ready
 348         comb += rst_l.r.eq(issue_i)
 349
 350         # create a latch/register for the operand
 351         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 352         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 353
 354         # and for LD
 355         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
 356         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 357
 358         # and for each input from the incoming src operands
 359         srl = []
 360         for i in range(self.n_src):
 361             name = "src_r%d" % i
 362             src_r = Signal(self.data_wid, name=name, reset_less=True)
 363             latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
 364             srl.append(src_r)
 365
 366         # and one for the output from the ADD (for the EA)
 367         addr_r = Signal(self.data_wid, reset_less=True)  # Effective Address
 368         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 369
 370         # select either zero or src1 if opcode says so
 371         op_is_z = oper_r.zero_a
 372         src1_or_z = Signal(self.data_wid, reset_less=True)
 373         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 374
 375         # select either immediate or src2 if opcode says so
 376         op_is_imm = oper_r.imm_data.imm_ok
 377         src2_or_imm = Signal(self.data_wid, reset_less=True)
 378         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 379
 380         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 381         sync += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
 382         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 383
 384         # decode bits of operand (latched)
 385         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 386         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 387         op_is_update = oper_r.update                                 # UPDATE
 388         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 389         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 390         comb += self.ld_o.eq(op_is_ld)
 391         comb += self.st_o.eq(op_is_st)
 392
 393         ############################
 394         # Control Signal calculation
 395
 396         # busy signal
 397         busy_o = self.busy_o
 398         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 399
 400         # 1st operand read-request only when zero not active
 401         # 2nd operand only needed when immediate is not active
 402         slg = Cat(op_is_z, op_is_imm)
 403         bro = Repl(self.busy_o, self.n_src)
 404         comb += self.rd.rel.eq(src_l.q & bro & ~slg & ~self.rdmaskn)
 405
 406         # note when the address-related read "go" signals are active
 407         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 408
 409         # alu input valid when 1st and 2nd ops done (or imm not active)
 410         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 411
 412         # 3rd operand only needed when operation is a store
 413         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 414
 415         # all reads done when alu is valid and 3rd operand needed
 416         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 417
 418         # address release only if addr ready, but Port must be idle
 419         comb += self.adr_rel_o.eq(alu_valid & adr_l.q & busy_o)
 420
 421         # store release when st ready *and* all operands read (and no shadow)
 422         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 423                                self.shadown_i)
 424
 425         # request write of LD result.  waits until shadow is dropped.
 426         comb += self.wr.rel[0].eq(rd_done & wri_l.q & busy_o & lod_l.qn &
 427                                   op_is_ld & self.shadown_i)
 428
 429         # request write of EA result only in update mode
 430         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 431                                   self.shadown_i)
 432
 433         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 434         comb += wr_any.eq(self.st.go | p_st_go | self.wr.go[0] | self.wr.go[1])
 435         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 436                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 437                      (lod_l.qn | op_is_st))
 438         comb += self.done_o.eq(wr_reset)
 439
 440         ######################
 441         # Data/Address outputs
 442
 443         # put the LD-output register directly onto the output bus on a go_write
 444         comb += self.data_o.data.eq(self.dest[0])
 445         with m.If(self.wr.go[0]):
 446             comb += self.dest[0].eq(ldd_r)
 447
 448         # "update" mode, put address out on 2nd go-write
 449         comb += self.addr_o.data.eq(self.dest[1])
 450         with m.If(op_is_update & self.wr.go[1]):
 451             comb += self.dest[1].eq(addr_r)
 452
 453         # need to look like MultiCompUnit: put wrmask out.
 454         # XXX may need to make this enable only when write active
 455         comb += self.wrmask.eq(bro & Cat(op_is_ld, op_is_update))
 456
 457         ###########################
 458         # PortInterface connections
 459         pi = self.pi
 460
 461         # connect to LD/ST PortInterface.
 462         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 463         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 464         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 465         # address
 466         comb += pi.addr.data.eq(addr_r)           # EA from adder
 467         comb += pi.addr.ok.eq(alu_ok & (lod_l.q | sto_l.q)) # "go do address stuff"
 468         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 469         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 470         # ld - ld gets latched in via lod_l
 471         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 472         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 473         # store - data goes in based on go_st
 474         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 475         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 476
 477         return m
 478
 479     def get_out(self, i):
 480         """make LDSTCompUnit look like RegSpecALUAPI"""
 481         if i == 0:
 482             return self.data_o
 483         if i == 1:
 484             return self.addr_o
 485         #return self.dest[i]
 486
 487     def __iter__(self):
 488         yield self.rd.go
 489         yield self.go_ad_i
 490         yield self.wr.go
 491         yield self.go_st_i
 492         yield self.issue_i
 493         yield self.shadown_i
 494         yield self.go_die_i
 495         yield from self.oper_i.ports()
 496         yield from self.src_i
 497         yield self.busy_o
 498         yield self.rd.rel
 499         yield self.adr_rel_o
 500         yield self.sto_rel_o
 501         yield self.wr.rel
 502         yield from self.data_o.ports()
 503         yield from self.addr_o.ports()
 504         yield self.load_mem_o
 505         yield self.stwd_mem_o
 506
 507     def ports(self):
 508         return list(self)
 509
 510
 511 def wait_for(sig, wait=True, test1st=False):
 512     v = (yield sig)
 513     print("wait for", sig, v, wait, test1st)
 514     if test1st and bool(v) == wait:
 515         return
 516     while True:
 517         yield
 518         v = (yield sig)
 519         #print("...wait for", sig, v)
 520         if bool(v) == wait:
 521             break
 522
 523
 524 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 525     print ("ST", src1, src2, src3, imm, imm_ok, update)
 526     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 527     yield dut.oper_i.data_len.eq(2) # half-word
 528     yield dut.src1_i.eq(src1)
 529     yield dut.src2_i.eq(src2)
 530     yield dut.src3_i.eq(src3)
 531     yield dut.oper_i.imm_data.imm.eq(imm)
 532     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 533     yield dut.oper_i.update.eq(update)
 534     yield dut.issue_i.eq(1)
 535     yield
 536     yield dut.issue_i.eq(0)
 537     yield
 538     if imm_ok:
 539         yield dut.rd.go.eq(0b101)
 540     else:
 541         yield dut.rd.go.eq(0b111)
 542     yield from wait_for(dut.rd.rel)
 543     yield dut.rd.go.eq(0)
 544
 545     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 546     #yield from wait_for(dut.adr_rel_o)
 547     #yield dut.ad.go.eq(1)
 548     #yield
 549     #yield dut.ad.go.eq(0)
 550
 551     if update:
 552         yield from wait_for(dut.wr.rel[1])
 553         yield dut.wr.go.eq(0b10)
 554         yield
 555         addr = yield dut.addr_o
 556         print ("addr", addr)
 557         yield dut.wr.go.eq(0)
 558     else:
 559         addr = None
 560
 561     yield from wait_for(dut.sto_rel_o)
 562     yield dut.go_st_i.eq(1)
 563     yield
 564     yield dut.go_st_i.eq(0)
 565     yield from wait_for(dut.busy_o, False)
 566     #wait_for(dut.stwd_mem_o)
 567     yield
 568     return addr
 569
 570
 571 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
 572     print ("LD", src1, src2, imm, imm_ok, update)
 573     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 574     yield dut.oper_i.data_len.eq(2) # half-word
 575     yield dut.src1_i.eq(src1)
 576     yield dut.src2_i.eq(src2)
 577     yield dut.oper_i.zero_a.eq(zero_a)
 578     yield dut.oper_i.imm_data.imm.eq(imm)
 579     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 580     yield dut.issue_i.eq(1)
 581     yield
 582     yield dut.issue_i.eq(0)
 583     yield
 584     rd = 0b00
 585     if not imm_ok:
 586         rd |= 0b10
 587     if not zero_a:
 588         rd |= 0b01
 589
 590     if rd:
 591         yield dut.rd.go.eq(rd)
 592         yield from wait_for(dut.rd.rel)
 593         yield dut.rd.go.eq(0)
 594
 595     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 596     #yield dut.ad.go.eq(1)
 597     #yield
 598     #yield dut.ad.go.eq(0)
 599
 600     if update:
 601         yield from wait_for(dut.wr.rel[1])
 602         yield dut.wr.go.eq(0b10)
 603         yield
 604         addr = yield dut.addr_o
 605         print ("addr", addr)
 606         yield dut.wr.go.eq(0)
 607     else:
 608         addr = None
 609
 610     yield from wait_for(dut.wr.rel[0], test1st=True)
 611     yield dut.wr.go.eq(1)
 612     yield
 613     data = yield dut.data_o
 614     print (data)
 615     yield dut.wr.go.eq(0)
 616     yield from wait_for(dut.busy_o)
 617     yield
 618     # wait_for(dut.stwd_mem_o)
 619     return data, addr
 620
 621
 622 def ldst_sim(dut):
 623
 624     ###################
 625     # immediate version
 626
 627     # two STs (different addresses)
 628     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 629     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 630     yield
 631     # two LDs (deliberately LD from the 1st address then 2nd)
 632     data, addr = yield from load(dut, 4, 0, 2)
 633     assert data == 0x0003, "returned %x" % data
 634     data, addr  = yield from load(dut, 2, 0, 2)
 635     assert data == 0x0009, "returned %x" % data
 636     yield
 637
 638     # indexed version
 639     yield from store(dut, 9, 5, 3, 0, imm_ok=False)
 640     data, addr = yield from load(dut, 9, 5, 0, imm_ok=False)
 641     assert data == 0x0003, "returned %x" % data
 642
 643     # update-immediate version
 644     addr = yield from store(dut, 9, 6, 3, 2, update=True)
 645     assert addr == 0x000b, "returned %x" % addr
 646
 647     # update-indexed version
 648     data, addr  = yield from load(dut, 9, 5, 0, imm_ok=False, update=True)
 649     assert data == 0x0003, "returned %x" % data
 650     assert addr == 0x000e, "returned %x" % addr
 651
 652     # immediate *and* zero version
 653     data, addr  = yield from load(dut, 1, 4, 8, imm_ok=True, zero_a=True)
 654     assert data == 0x0008, "returned %x" % data
 655
 656
 657 class TestLDSTCompUnit(LDSTCompUnit):
 658
 659     def __init__(self, rwid):
 660         from soc.experiment.l0_cache import TstL0CacheBuffer
 661         self.l0 = l0 = TstL0CacheBuffer()
 662         pi = l0.l0.dports[0].pi
 663         LDSTCompUnit.__init__(self, pi, rwid, 4)
 664
 665     def elaborate(self, platform):
 666         m = LDSTCompUnit.elaborate(self, platform)
 667         m.submodules.l0 = self.l0
 668         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 669         return m
 670
 671
 672 def test_scoreboard():
 673
 674     dut = TestLDSTCompUnit(16)
 675     vl = rtlil.convert(dut, ports=dut.ports())
 676     with open("test_ldst_comp.il", "w") as f:
 677         f.write(vl)
 678
 679     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 680
 681
 682 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 683
 684     def __init__(self):
 685         from soc.experiment.l0_cache import TstL0CacheBuffer
 686         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 687         regspec = LDSTPipeSpec.regspec
 688         self.l0 = l0 = TstL0CacheBuffer()
 689         pi = l0.l0.dports[0].pi
 690         LDSTCompUnit.__init__(self, pi, regspec, 4)
 691
 692     def elaborate(self, platform):
 693         m = LDSTCompUnit.elaborate(self, platform)
 694         m.submodules.l0 = self.l0
 695         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 696         return m
 697
 698
 699 def test_scoreboard_regspec():
 700
 701     dut = TestLDSTCompUnitRegSpec()
 702     vl = rtlil.convert(dut, ports=dut.ports())
 703     with open("test_ldst_comp.il", "w") as f:
 704         f.write(vl)
 705
 706     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 707
 708
 709 if __name__ == '__main__':
 710     test_scoreboard_regspec()
 711     test_scoreboard()