1 """ LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
60 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
62 Links including to walk-through videos:
63 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * https://bugs.libre-soc.org/show_bug.cgi?id=302
70 * EA - Effective Address
75 from nmigen
.compat
.sim
import run_simulation
76 from nmigen
.cli
import verilog
, rtlil
77 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
78 from nmigen
.hdl
.rec
import Record
, Layout
80 from nmutil
.latch
import SRLatch
, latchregister
82 from soc
.experiment
.compalu_multi
import go_record
83 from soc
.experiment
.l0_cache
import PortInterface
84 from soc
.experiment
.testmem
import TestMemory
85 from soc
.decoder
.power_enums
import InternalOp
87 from soc
.decoder
.power_enums
import InternalOp
, Function
90 class CompLDSTOpSubset(Record
):
93 a copy of the relevant subset information from Decode2Execute1Type
94 needed for LD/ST operations. use with eq_from_execute1 (below) to
97 def __init__(self
, name
=None):
98 layout
= (('insn_type', InternalOp
),
99 ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
102 ('data_len', 4), # TODO: should be in separate CompLDSTSubset
107 Record
.__init
__(self
, Layout(layout
), name
=name
)
109 # grrr. Record does not have kwargs
110 self
.insn_type
.reset_less
= True
111 self
.is_32bit
.reset_less
= True
112 self
.is_signed
.reset_less
= True
113 self
.data_len
.reset_less
= True
114 self
.byte_reverse
.reset_less
= True
115 self
.sign_extend
.reset_less
= True
116 self
.update
.reset_less
= True
118 def eq_from_execute1(self
, other
):
119 """ use this to copy in from Decode2Execute1Type
122 for fname
, sig
in self
.fields
.items():
123 eqfrom
= other
.fields
[fname
]
124 res
.append(sig
.eq(eqfrom
))
128 return [self
.insn_type
,
138 class LDSTCompUnit(Elaboratable
):
139 """LOAD / STORE Computation Unit
144 * :pi: a PortInterface to the memory subsystem (read-write capable)
145 * :rwid: register width
146 * :awid: address width
150 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
154 * :data_o: Dest out (LD) - managed by wr[0] go/req
155 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
156 * :addr_exc_o: Address/Data Exception occurred. LD/ST must terminate
158 TODO: make addr_exc_o a data-type rather than a single-bit signal
164 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
165 * :issue_i: LD/ST is being "issued".
166 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
167 * :go_rd_i: read is being actioned (latches in src regs)
168 * :go_wr_i: write mode (exactly like ALU CompUnit)
169 * :go_ad_i: address is being actioned (triggers actual mem LD)
170 * :go_st_i: store is being actioned (triggers actual mem STORE)
171 * :go_die_i: resets the unit back to "wait for issue"
173 Control Signals (Out)
174 ---------------------
176 * :busy_o: function unit is busy
177 * :rd_rel_o: request src1/src2
178 * :adr_rel_o: request address (from mem)
179 * :sto_rel_o: request store (to mem)
180 * :req_rel_o: request write (result)
181 * :load_mem_o: activate memory LOAD
182 * :stwd_mem_o: activate memory STORE
184 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
185 in a single cycle and the CompUnit set back to doing another op.
186 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
187 depending on whether the operation is a ST or LD.
190 def __init__(self
, pi
, rwid
=64, awid
=48, debugtest
=False):
194 self
.debugtest
= debugtest
196 # POWER-compliant LD/ST has index and update: *fixed* number of ports
197 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
198 self
.n_dst
= n_dst
= 2 # RA, RT/RS
200 # set up array of src and dest signals
202 for i
in range(n_src
):
203 j
= i
+ 1 # name numbering to match src1/src2
204 src
.append(Signal(rwid
, name
="src%d_i" % j
, reset_less
=True))
207 for i
in range(n_dst
):
208 j
= i
+ 1 # name numbering to match dest1/2...
209 dst
.append(Signal(rwid
, name
="dest%d_o" % j
, reset_less
=True))
211 # control (dual in/out)
212 self
.rd
= go_record(n_src
, name
="rd") # read in, req out
213 self
.wr
= go_record(n_dst
, name
="wr") # write in, req out
214 self
.ad
= go_record(1, name
="ad") # address go in, req out
215 self
.st
= go_record(1, name
="st") # store go in, req out
217 self
.go_rd_i
= self
.rd
.go
# temporary naming
218 self
.go_wr_i
= self
.wr
.go
# temporary naming
219 self
.rd_rel_o
= self
.rd
.rel
# temporary naming
220 self
.req_rel_o
= self
.wr
.rel
# temporary naming
222 self
.go_ad_i
= self
.ad
.go
# temp naming: go address in
223 self
.go_st_i
= self
.st
.go
# temp naming: go store in
226 self
.issue_i
= Signal(reset_less
=True) # fn issue in
227 self
.shadown_i
= Signal(reset
=1) # shadow function, defaults to ON
228 self
.go_die_i
= Signal() # go die (reset)
230 # operation / data input
231 self
.oper_i
= CompLDSTOpSubset() # operand
232 self
.src_i
= Array(src
)
233 self
.src1_i
= src
[0] # oper1 in: RA
234 self
.src2_i
= src
[1] # oper2 in: RB
235 self
.src3_i
= src
[2] # oper2 in: RC (RS)
238 self
.busy_o
= Signal(reset_less
=True) # fn busy out
239 self
.done_o
= Signal(reset_less
=True) # final release signal
240 # TODO (see bug #302)
241 self
.addr_exc_o
= Signal(reset_less
=True) # address exception
242 self
.dest
= Array(dst
)
243 self
.data_o
= dst
[0] # Dest1 out: RT
244 self
.addr_o
= dst
[1] # Address out (LD or ST) - Update => RA
246 self
.adr_rel_o
= self
.ad
.rel
# request address (from mem)
247 self
.sto_rel_o
= self
.st
.rel
# request store (to mem)
249 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
250 self
.st_o
= Signal(reset_less
=True) # operation is a ST
252 # hmm... are these necessary?
253 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
254 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
256 def elaborate(self
, platform
):
262 issue_i
= self
.issue_i
264 #####################
265 # latches for the FSM.
266 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
267 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
268 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
269 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
270 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
271 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
272 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
273 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
274 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
280 op_is_ld
= Signal(reset_less
=True)
281 op_is_st
= Signal(reset_less
=True)
283 # ALU/LD data output control
284 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
285 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
286 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
287 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
288 wr_any
= Signal(reset_less
=True) # any write (incl. store)
289 rda_any
= Signal(reset_less
=True) # any read for address ops
290 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
291 wr_reset
= Signal(reset_less
=True) # final reset condition
294 alu_o
= Signal(self
.rwid
, reset_less
=True)
295 ldd_o
= Signal(self
.rwid
, reset_less
=True)
297 # select immediate or src2 reg to add
298 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
299 src_sel
= Signal(reset_less
=True)
301 ##############################
302 # reset conditions for latches
304 # temporaries (also convenient when debugging)
305 reset_o
= Signal(reset_less
=True) # reset opcode
306 reset_w
= Signal(reset_less
=True) # reset write
307 reset_u
= Signal(reset_less
=True) # reset update
308 reset_a
= Signal(reset_less
=True) # reset adr latch
309 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
310 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
311 reset_s
= Signal(reset_less
=True) # reset store
313 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
314 comb
+= reset_o
.eq(wr_reset | self
.go_die_i
) # opcode reset
315 comb
+= reset_w
.eq(self
.wr
.go
[0] | self
.go_die_i
) # write reg 1
316 comb
+= reset_u
.eq(self
.wr
.go
[1] | self
.go_die_i
) # update (reg 2)
317 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
318 comb
+= reset_r
.eq(self
.rd
.go |
Repl(self
.go_die_i
, self
.n_src
))
319 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
321 ##########################
322 # FSM implemented through sequence of latches. approximately this:
324 # - src_l[0] : operands
326 # - alu_l : looks after add of src1/2/imm (EA)
327 # - adr_l : waits for add (EA)
328 # - upd_l : waits for adr and Regfile (port 2)
330 # - lod_l : waits for adr (EA) and for LD Data
331 # - wri_l : waits for LD Data and Regfile (port 1)
332 # - st_l : waits for alu and operand2
333 # - rst_l : waits for all FSM paths to converge.
334 # NOTE: use sync to stop combinatorial loops.
336 # opcode latch - inverted so that busy resets to 0
337 # note this MUST be sync so as to avoid a combinatorial loop
338 # between busy_o and issue_i on the reset latch (rst_l)
339 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
340 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
343 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
344 sync
+= src_l
.r
.eq(reset_r
)
347 comb
+= alu_l
.s
.eq(reset_i
)
348 comb
+= alu_l
.r
.eq(alu_ok
& ~rda_any
)
351 comb
+= adr_l
.s
.eq(reset_i | ld_ok
)
352 sync
+= adr_l
.r
.eq(reset_a
)
355 comb
+= lod_l
.s
.eq(reset_i
)
356 comb
+= lod_l
.r
.eq(ld_ok
)
359 comb
+= wri_l
.s
.eq(issue_i
)
360 sync
+= wri_l
.r
.eq(reset_w
)
362 # update-mode operand latch (EA written to reg 2)
363 sync
+= upd_l
.s
.eq(alu_l
.s
)
364 sync
+= upd_l
.r
.eq(reset_u
)
367 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
368 comb
+= sto_l
.r
.eq(reset_s
)
371 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
372 comb
+= rst_l
.r
.eq(issue_i
)
374 # create a latch/register for the operand
375 oper_r
= CompLDSTOpSubset() # Dest register
376 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, name
="oper_r")
379 ldd_r
= Signal(self
.rwid
, reset_less
=True) # Dest register
380 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
382 # and for each input from the incoming src operands
384 for i
in range(self
.n_src
):
386 src_r
= Signal(self
.rwid
, name
=name
, reset_less
=True)
387 latchregister(m
, self
.src_i
[i
], src_r
, src_l
.q
[i
], name
)
390 # and one for the output from the ADD (for the EA)
391 addr_r
= Signal(self
.rwid
, reset_less
=True) # Effective Address Latch
392 latchregister(m
, alu_o
, addr_r
, alu_l
.qn
, "ea_r")
394 # select either immediate or src2 if opcode says so
395 op_is_imm
= oper_r
.imm_data
.imm_ok
396 src2_or_imm
= Signal(self
.rwid
, reset_less
=True)
397 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
, srl
[1]))
399 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
400 sync
+= alu_o
.eq(srl
[0] + src2_or_imm
) # actual EA
401 sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
403 # decode bits of operand (latched)
404 comb
+= op_is_st
.eq(oper_r
.insn_type
== InternalOp
.OP_STORE
) # ST
405 comb
+= op_is_ld
.eq(oper_r
.insn_type
== InternalOp
.OP_LOAD
) # LD
406 op_is_update
= oper_r
.update
# UPDATE
407 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
408 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
409 comb
+= self
.ld_o
.eq(op_is_ld
)
410 comb
+= self
.st_o
.eq(op_is_st
)
412 ############################
413 # Control Signal calculation
417 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
419 # 1st operand read-request is simple: always need it
420 comb
+= self
.rd
.rel
[0].eq(src_l
.q
[0] & busy_o
)
422 # 2nd operand only needed when immediate is not active
423 comb
+= self
.rd
.rel
[1].eq(src_l
.q
[1] & busy_o
& ~op_is_imm
)
425 # note when the address-related read "go" signals are active
426 comb
+= rda_any
.eq(self
.rd
.go
[0] | self
.rd
.go
[1])
428 # alu input valid when 1st and 2nd ops done (or imm not active)
429 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel
[0] | self
.rd
.rel
[1]))
431 # 3rd operand only needed when operation is a store
432 comb
+= self
.rd
.rel
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
434 # all reads done when alu is valid and 3rd operand needed
435 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel
[2])
437 # address release only if addr ready, but Port must be idle
438 comb
+= self
.adr_rel_o
.eq(adr_l
.q
& busy_o
)
440 # store release when st ready *and* all operands read (and no shadow)
441 comb
+= self
.st
.rel
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
444 # request write of LD result. waits until shadow is dropped.
445 comb
+= self
.wr
.rel
[0].eq(wri_l
.q
& busy_o
& lod_l
.qn
& op_is_ld
&
448 # request write of EA result only in update mode
449 comb
+= self
.wr
.rel
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
452 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
453 comb
+= wr_any
.eq(self
.st
.go | self
.wr
.go
[0] | self
.wr
.go
[1])
454 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
& wr_any
&
455 ~
(self
.st
.rel | self
.wr
.rel
[0] | self
.wr
.rel
[1]) &
456 (lod_l
.qn | op_is_st
))
457 comb
+= self
.done_o
.eq(wr_reset
)
459 ######################
460 # Data/Address outputs
462 # put the LD-output register directly onto the output bus on a go_write
463 with m
.If(self
.wr
.go
[0]):
464 comb
+= self
.data_o
.eq(ldd_r
)
466 # "update" mode, put address out on 2nd go-write
467 with m
.If(op_is_update
& self
.wr
.go
[1]):
468 comb
+= self
.addr_o
.eq(addr_r
)
470 ###########################
471 # PortInterface connections
474 # connect to LD/ST PortInterface.
475 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
476 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
477 comb
+= pi
.op
.eq(self
.oper_i
) # op details (not all needed)
479 comb
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
480 comb
+= pi
.addr
.ok
.eq(adr_l
.qn | self
.ad
.go
) # "go do address stuff"
481 comb
+= self
.addr_exc_o
.eq(pi
.addr_exc_o
) # exception occurred
482 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
483 # ld - ld gets latched in via lod_l
484 comb
+= ldd_o
.eq(pi
.ld
.data
) # ld data goes into ld reg (above)
485 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
486 # store - data goes in based on go_st
487 comb
+= pi
.st
.data
.eq(srl
[2]) # 3rd operand latch
488 comb
+= pi
.st
.ok
.eq(self
.st
.go
) # go store signals st data valid
500 yield from self
.oper_i
.ports()
501 yield from self
.src_i
509 yield self
.load_mem_o
510 yield self
.stwd_mem_o
516 def wait_for(sig
, wait
=True, test1st
=False):
518 print("wait for", sig
, v
)
519 if test1st
and bool(v
) == wait
:
524 #print("...wait for", sig, v)
529 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False):
530 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_STORE
)
531 yield dut
.src1_i
.eq(src1
)
532 yield dut
.src2_i
.eq(src2
)
533 yield dut
.src3_i
.eq(src3
)
534 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
535 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
536 yield dut
.oper_i
.update
.eq(update
)
537 yield dut
.issue_i
.eq(1)
539 yield dut
.issue_i
.eq(0)
541 yield dut
.rd
.go
.eq(0b111)
542 yield from wait_for(dut
.rd
.rel
)
543 yield dut
.rd
.go
.eq(0)
545 yield from wait_for(dut
.adr_rel_o
)
546 yield dut
.ad
.go
.eq(1)
548 yield dut
.ad
.go
.eq(0)
551 yield from wait_for(dut
.wr
.rel
[1])
552 yield dut
.wr
.go
.eq(0b10)
554 addr
= yield dut
.addr_o
556 yield dut
.wr
.go
.eq(0)
560 yield from wait_for(dut
.sto_rel_o
)
561 yield dut
.go_st_i
.eq(1)
563 yield dut
.go_st_i
.eq(0)
564 yield from wait_for(dut
.busy_o
, False)
565 #wait_for(dut.stwd_mem_o)
570 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False):
571 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_LOAD
)
572 yield dut
.src1_i
.eq(src1
)
573 yield dut
.src2_i
.eq(src2
)
574 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
575 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
576 yield dut
.issue_i
.eq(1)
578 yield dut
.issue_i
.eq(0)
581 yield dut
.rd
.go
.eq(0b01)
583 yield dut
.rd
.go
.eq(0b11)
584 yield from wait_for(dut
.rd
.rel
)
585 yield dut
.rd
.go
.eq(0)
587 yield from wait_for(dut
.adr_rel_o
)
588 yield dut
.ad
.go
.eq(1)
590 yield dut
.ad
.go
.eq(0)
593 yield from wait_for(dut
.wr
.rel
[1])
594 yield dut
.wr
.go
.eq(0b10)
596 addr
= yield dut
.addr_o
598 yield dut
.wr
.go
.eq(0)
602 yield from wait_for(dut
.wr
.rel
[0], test1st
=True)
603 yield dut
.wr
.go
.eq(1)
605 data
= yield dut
.data_o
607 yield dut
.wr
.go
.eq(0)
608 yield from wait_for(dut
.busy_o
)
610 # wait_for(dut.stwd_mem_o)
614 def scoreboard_sim(dut
):
619 # two STs (different addresses)
620 yield from store(dut
, 4, 0, 3, 2)
621 yield from store(dut
, 2, 0, 9, 2)
623 # two LDs (deliberately LD from the 1st address then 2nd)
624 data
, addr
= yield from load(dut
, 4, 0, 2)
625 assert data
== 0x0003, "returned %x" % data
626 data
, addr
= yield from load(dut
, 2, 0, 2)
627 assert data
== 0x0009, "returned %x" % data
631 yield from store(dut
, 4, 5, 3, 0, imm_ok
=False)
632 data
, addr
= yield from load(dut
, 4, 5, 0, imm_ok
=False)
633 assert data
== 0x0003, "returned %x" % data
635 # update-immediate version
636 addr
= yield from store(dut
, 4, 6, 3, 2, update
=True)
637 assert addr
== 0x0006, "returned %x" % addr
639 # update-indexed version
640 data
, addr
= yield from load(dut
, 4, 5, 0, imm_ok
=False, update
=True)
641 assert addr
== 0x0009, "returned %x" % addr
643 class TestLDSTCompUnit(LDSTCompUnit
):
645 def __init__(self
, rwid
):
646 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
647 self
.l0
= l0
= TstL0CacheBuffer()
648 pi
= l0
.l0
.dports
[0].pi
649 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
651 def elaborate(self
, platform
):
652 m
= LDSTCompUnit
.elaborate(self
, platform
)
653 m
.submodules
.l0
= self
.l0
657 def test_scoreboard():
659 dut
= TestLDSTCompUnit(16)
660 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
661 with
open("test_ldst_comp.il", "w") as f
:
664 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_ldst_comp.vcd')
667 if __name__
== '__main__':