src/soc/experiment/compldst_multi.py

   1 """LOAD / STORE Computation Unit.
   2
   3 This module covers POWER9-compliant Load and Store operations,
   4 with selection on each between immediate and indexed mode as
   5 options for the calculation of the Effective Address (EA),
   6 and also "update" mode which optionally stores that EA into
   7 an additional register.
   8
   9 ----
  10 Note: it took 15 attempts over several weeks to redraw the diagram
  11 needed to capture this FSM properly.  To understand it fully, please
  12 take the time to review the links, video, and diagram.
  13 ----
  14
  15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16 compute the "Effective Address", and, when ready the operand (src3_i)
  17 is stored in the computed address (passed through to the PortInterface)
  18
  19 Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20 and (as long as there was no exception) the data comes out (at any
  21 time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23 Both LD and ST may request that the address be computed from summing
  24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25 the immediate (from the opcode).
  26
  27 Both LD and ST may also request "update" mode (op_is_update) which
  28 activates the use of Go_Write[1] to control storage of the EA into
  29 a *second* operand in the register file.
  30
  31 Thus this module has *TWO* write-requests to the register file and
  32 *THREE* read-requests to the register file (not all at the same time!)
  33 The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47 the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59 Full diagram:
  60
  61     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  62
  63 Links including to walk-through videos:
  64
  65     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  66     * http://libre-soc.org/openpower/isa/fixedload
  67     * http://libre-soc.org/openpower/isa/fixedstore
  68
  69 Related Bugreports:
  70
  71     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  72     * https://bugs.libre-soc.org/show_bug.cgi?id=216
  73
  74 Terminology:
  75
  76     * EA - Effective Address
  77     * LD - Load
  78     * ST - Store
  79 """
  80
  81 from nmigen.compat.sim import run_simulation
  82 from nmigen.cli import verilog, rtlil
  83 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  84 from nmigen.hdl.rec import Record, Layout
  85
  86 from nmutil.latch import SRLatch, latchregister
  87
  88 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  89 from soc.experiment.l0_cache import PortInterface
  90 from soc.experiment.testmem import TestMemory
  91
  92 from soc.decoder.power_enums import InternalOp, Function
  93 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  94
  95
  96 class LDSTCompUnitRecord(CompUnitRecord):
  97     def __init__(self, rwid, name=None):
  98         CompUnitRecord.__init__(self, CompLDSTOpSubset, rwid,
  99                                 n_src=3, n_dst=2, name=name)
 100
 101         self.ad = go_record(1, name="ad") # address go in, req out
 102         self.st = go_record(1, name="st") # store go in, req out
 103
 104         self.addr_exc_o = Signal(reset_less=True)   # address exception
 105
 106         self.ld_o = Signal(reset_less=True)  # operation is a LD
 107         self.st_o = Signal(reset_less=True)  # operation is a ST
 108
 109         # hmm... are these necessary?
 110         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 111         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 112
 113
 114 class LDSTCompUnit(Elaboratable):
 115     """LOAD / STORE Computation Unit
 116
 117     Inputs
 118     ------
 119
 120     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 121     * :rwid:   register width
 122     * :awid:   address width
 123
 124     Data inputs
 125     -----------
 126     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 127
 128     Data (outputs)
 129     --------------
 130     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 131     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 132     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 133
 134     TODO: make addr_exc_o a data-type rather than a single-bit signal
 135           (see bug #302)
 136
 137     Control Signals (In)
 138     --------------------
 139
 140     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 141     * :issue_i:    LD/ST is being "issued".
 142     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 143     * :go_rd_i:    read is being actioned (latches in src regs)
 144     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 145     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 146     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 147     * :go_die_i:   resets the unit back to "wait for issue"
 148
 149     Control Signals (Out)
 150     ---------------------
 151
 152     * :busy_o:      function unit is busy
 153     * :rd_rel_o:    request src1/src2
 154     * :adr_rel_o:   request address (from mem)
 155     * :sto_rel_o:   request store (to mem)
 156     * :req_rel_o:   request write (result)
 157     * :load_mem_o:  activate memory LOAD
 158     * :stwd_mem_o:  activate memory STORE
 159
 160     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 161     in a single cycle and the CompUnit set back to doing another op.
 162     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 163     depending on whether the operation is a ST or LD.
 164     """
 165
 166     def __init__(self, pi=None, rwid=64, awid=48, debugtest=False):
 167         self.rwid = rwid
 168         self.awid = awid
 169         self.pi = pi
 170         self.cu = cu = LDSTCompUnitRecord(rwid)
 171         self.debugtest = debugtest
 172
 173         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 174         self.n_src = n_src = 3   # RA, RB, RT/RS
 175         self.n_dst = n_dst = 2 # RA, RT/RS
 176
 177         # set up array of src and dest signals
 178         for i in range(n_src):
 179             j = i + 1 # name numbering to match src1/src2
 180             name = "src%d_i" % j
 181             setattr(self, name, getattr(cu, name))
 182
 183         dst = []
 184         for i in range(n_dst):
 185             j = i + 1 # name numbering to match dest1/2...
 186             name = "dest%d_o" % j
 187             setattr(self, name, getattr(cu, name))
 188
 189         # convenience names
 190         self.rd = cu.rd
 191         self.wr = cu.wr
 192         self.ad = cu.ad
 193         self.st = cu.st
 194
 195         self.go_rd_i = self.rd.go # temporary naming
 196         self.go_wr_i = self.wr.go # temporary naming
 197         self.go_ad_i = self.ad.go # temp naming: go address in
 198         self.go_st_i = self.st.go  # temp naming: go store in
 199
 200         self.rd_rel_o = self.rd.rel # temporary naming
 201         self.req_rel_o = self.wr.rel # temporary naming
 202         self.adr_rel_o = self.ad.rel  # request address (from mem)
 203         self.sto_rel_o = self.st.rel  # request store (to mem)
 204
 205         self.issue_i = cu.issue_i
 206         self.shadown_i = cu.shadown_i
 207         self.go_die_i = cu.go_die_i
 208
 209         self.oper_i = cu.oper_i
 210         self.src_i = cu._src_i
 211         self.dest = cu._dest
 212
 213         self.data_o = self.dest[0]  # Dest1 out: RT
 214         self.addr_o = self.dest[1]  # Address out (LD or ST) - Update => RA
 215         self.addr_exc_o = cu.addr_exc_o
 216         self.done_o = cu.done_o
 217         self.busy_o = cu.busy_o
 218
 219         self.ld_o = cu.ld_o
 220         self.st_o = cu.st_o
 221
 222         self.load_mem_o = cu.load_mem_o
 223         self.stwd_mem_o = cu.stwd_mem_o
 224
 225         # HACK: get data width from dest[0].  this is used across the board
 226         # (it really shouldn't be)
 227         self.data_wid = self.dest[0].shape()
 228
 229     def elaborate(self, platform):
 230         m = Module()
 231
 232         # temp/convenience
 233         comb = m.d.comb
 234         sync = m.d.sync
 235         issue_i = self.issue_i
 236
 237         #####################
 238         # latches for the FSM.
 239         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 240         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 241         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 242         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 243         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 244         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 245         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 246         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 247         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 248
 249         ####################
 250         # signals
 251
 252         # opcode decode
 253         op_is_ld = Signal(reset_less=True)
 254         op_is_st = Signal(reset_less=True)
 255
 256         # ALU/LD data output control
 257         alu_valid = Signal(reset_less=True) # ALU operands are valid
 258         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 259         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 260         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 261         wr_any = Signal(reset_less=True)    # any write (incl. store)
 262         rda_any = Signal(reset_less=True)   # any read for address ops
 263         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 264         wr_reset = Signal(reset_less=True)  # final reset condition
 265
 266         # LD and ALU out
 267         alu_o = Signal(self.data_wid, reset_less=True)
 268         ldd_o = Signal(self.data_wid, reset_less=True)
 269
 270         ##############################
 271         # reset conditions for latches
 272
 273         # temporaries (also convenient when debugging)
 274         reset_o = Signal(reset_less=True)             # reset opcode
 275         reset_w = Signal(reset_less=True)             # reset write
 276         reset_u = Signal(reset_less=True)             # reset update
 277         reset_a = Signal(reset_less=True)             # reset adr latch
 278         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 279         reset_r = Signal(self.n_src, reset_less=True) # reset src
 280         reset_s = Signal(reset_less=True)             # reset store
 281
 282         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 283         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 284         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 285         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 286         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 287         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 288         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 289
 290         ##########################
 291         # FSM implemented through sequence of latches.  approximately this:
 292         # - opc_l       : opcode
 293         #    - src_l[0] : operands
 294         #    - src_l[1]
 295         #       - alu_l : looks after add of src1/2/imm (EA)
 296         #       - adr_l : waits for add (EA)
 297         #       - upd_l : waits for adr and Regfile (port 2)
 298         #    - src_l[2] : ST
 299         # - lod_l       : waits for adr (EA) and for LD Data
 300         # - wri_l       : waits for LD Data and Regfile (port 1)
 301         # - st_l        : waits for alu and operand2
 302         # - rst_l       : waits for all FSM paths to converge.
 303         # NOTE: use sync to stop combinatorial loops.
 304
 305         # opcode latch - inverted so that busy resets to 0
 306         # note this MUST be sync so as to avoid a combinatorial loop
 307         # between busy_o and issue_i on the reset latch (rst_l)
 308         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 309         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 310
 311         # src operand latch
 312         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 313         sync += src_l.r.eq(reset_r)
 314
 315         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 316         comb += alu_l.s.eq(reset_i)
 317         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 318
 319         # addr latch
 320         comb += adr_l.s.eq(reset_i)
 321         sync += adr_l.r.eq(reset_a)
 322
 323         # ld latch
 324         comb += lod_l.s.eq(reset_i)
 325         comb += lod_l.r.eq(ld_ok)
 326
 327         # dest operand latch
 328         comb += wri_l.s.eq(issue_i)
 329         sync += wri_l.r.eq(reset_w)
 330
 331         # update-mode operand latch (EA written to reg 2)
 332         sync += upd_l.s.eq(reset_i)
 333         sync += upd_l.r.eq(reset_u)
 334
 335         # store latch
 336         comb += sto_l.s.eq(addr_ok & op_is_st)
 337         comb += sto_l.r.eq(reset_s)
 338
 339         # reset latch
 340         comb += rst_l.s.eq(addr_ok) # start when address is ready
 341         comb += rst_l.r.eq(issue_i)
 342
 343         # create a latch/register for the operand
 344         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 345         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 346
 347         # and for LD
 348         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
 349         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 350
 351         # and for each input from the incoming src operands
 352         srl = []
 353         for i in range(self.n_src):
 354             name = "src_r%d" % i
 355             src_r = Signal(self.data_wid, name=name, reset_less=True)
 356             latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
 357             srl.append(src_r)
 358
 359         # and one for the output from the ADD (for the EA)
 360         addr_r = Signal(self.data_wid, reset_less=True)  # Effective Address
 361         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 362
 363         # select either zero or src1 if opcode says so
 364         op_is_z = oper_r.zero_a
 365         src1_or_z = Signal(self.data_wid, reset_less=True)
 366         m.d.comb += src1_or_z.eq(Mux(op_is_z, 0, srl[0]))
 367
 368         # select either immediate or src2 if opcode says so
 369         op_is_imm = oper_r.imm_data.imm_ok
 370         src2_or_imm = Signal(self.data_wid, reset_less=True)
 371         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 372
 373         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 374         sync += alu_o.eq(src1_or_z + src2_or_imm) # actual EA
 375         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 376
 377         # decode bits of operand (latched)
 378         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 379         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 380         op_is_update = oper_r.update                                 # UPDATE
 381         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 382         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 383         comb += self.ld_o.eq(op_is_ld)
 384         comb += self.st_o.eq(op_is_st)
 385
 386         ############################
 387         # Control Signal calculation
 388
 389         # busy signal
 390         busy_o = self.busy_o
 391         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 392
 393         # 1st operand read-request only when zero not active
 394         comb += self.rd.rel[0].eq(src_l.q[0] & busy_o & ~op_is_z)
 395
 396         # 2nd operand only needed when immediate is not active
 397         comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
 398
 399         # note when the address-related read "go" signals are active
 400         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 401
 402         # alu input valid when 1st and 2nd ops done (or imm not active)
 403         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 404
 405         # 3rd operand only needed when operation is a store
 406         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 407
 408         # all reads done when alu is valid and 3rd operand needed
 409         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 410
 411         # address release only if addr ready, but Port must be idle
 412         comb += self.adr_rel_o.eq(adr_l.q & busy_o)
 413
 414         # store release when st ready *and* all operands read (and no shadow)
 415         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 416                                self.shadown_i)
 417
 418         # request write of LD result.  waits until shadow is dropped.
 419         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 420                                   self.shadown_i)
 421
 422         # request write of EA result only in update mode
 423         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 424                                   self.shadown_i)
 425
 426         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 427         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 428         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 429                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 430                      (lod_l.qn | op_is_st))
 431         comb += self.done_o.eq(wr_reset)
 432
 433         ######################
 434         # Data/Address outputs
 435
 436         # put the LD-output register directly onto the output bus on a go_write
 437         with m.If(self.wr.go[0]):
 438             comb += self.data_o.eq(ldd_r)
 439
 440         # "update" mode, put address out on 2nd go-write
 441         with m.If(op_is_update & self.wr.go[1]):
 442             comb += self.addr_o.eq(addr_r)
 443
 444         ###########################
 445         # PortInterface connections
 446         pi = self.pi
 447
 448         # connect to LD/ST PortInterface.
 449         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 450         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 451         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 452         # address
 453         comb += pi.addr.data.eq(addr_r)           # EA from adder
 454         comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
 455         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 456         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 457         # ld - ld gets latched in via lod_l
 458         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 459         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 460         # store - data goes in based on go_st
 461         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 462         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 463
 464         return m
 465
 466     def __iter__(self):
 467         yield self.rd.go
 468         yield self.go_ad_i
 469         yield self.wr.go
 470         yield self.go_st_i
 471         yield self.issue_i
 472         yield self.shadown_i
 473         yield self.go_die_i
 474         yield from self.oper_i.ports()
 475         yield from self.src_i
 476         yield self.busy_o
 477         yield self.rd.rel
 478         yield self.adr_rel_o
 479         yield self.sto_rel_o
 480         yield self.wr.rel
 481         yield self.data_o
 482         yield self.addr_o
 483         yield self.load_mem_o
 484         yield self.stwd_mem_o
 485
 486     def ports(self):
 487         return list(self)
 488
 489
 490 def wait_for(sig, wait=True, test1st=False):
 491     v = (yield sig)
 492     print("wait for", sig, v, wait, test1st)
 493     if test1st and bool(v) == wait:
 494         return
 495     while True:
 496         yield
 497         v = (yield sig)
 498         #print("...wait for", sig, v)
 499         if bool(v) == wait:
 500             break
 501
 502
 503 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 504     print ("ST", src1, src2, src3, imm, imm_ok, update)
 505     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 506     yield dut.src1_i.eq(src1)
 507     yield dut.src2_i.eq(src2)
 508     yield dut.src3_i.eq(src3)
 509     yield dut.oper_i.imm_data.imm.eq(imm)
 510     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 511     yield dut.oper_i.update.eq(update)
 512     yield dut.issue_i.eq(1)
 513     yield
 514     yield dut.issue_i.eq(0)
 515     yield
 516     if imm_ok:
 517         yield dut.rd.go.eq(0b101)
 518     else:
 519         yield dut.rd.go.eq(0b111)
 520     yield from wait_for(dut.rd.rel)
 521     yield dut.rd.go.eq(0)
 522
 523     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 524     #yield from wait_for(dut.adr_rel_o)
 525     #yield dut.ad.go.eq(1)
 526     #yield
 527     #yield dut.ad.go.eq(0)
 528
 529     if update:
 530         yield from wait_for(dut.wr.rel[1])
 531         yield dut.wr.go.eq(0b10)
 532         yield
 533         addr = yield dut.addr_o
 534         print ("addr", addr)
 535         yield dut.wr.go.eq(0)
 536     else:
 537         addr = None
 538
 539     yield from wait_for(dut.sto_rel_o)
 540     yield dut.go_st_i.eq(1)
 541     yield
 542     yield dut.go_st_i.eq(0)
 543     yield from wait_for(dut.busy_o, False)
 544     #wait_for(dut.stwd_mem_o)
 545     yield
 546     return addr
 547
 548
 549 def load(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False):
 550     print ("LD", src1, src2, imm, imm_ok, update)
 551     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 552     yield dut.src1_i.eq(src1)
 553     yield dut.src2_i.eq(src2)
 554     yield dut.oper_i.zero_a.eq(zero_a)
 555     yield dut.oper_i.imm_data.imm.eq(imm)
 556     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 557     yield dut.issue_i.eq(1)
 558     yield
 559     yield dut.issue_i.eq(0)
 560     yield
 561     rd = 0b00
 562     if not imm_ok:
 563         rd |= 0b10
 564     if not zero_a:
 565         rd |= 0b01
 566
 567     if rd:
 568         yield dut.rd.go.eq(rd)
 569         yield from wait_for(dut.rd.rel)
 570         yield dut.rd.go.eq(0)
 571
 572     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 573     #yield dut.ad.go.eq(1)
 574     #yield
 575     #yield dut.ad.go.eq(0)
 576
 577     if update:
 578         yield from wait_for(dut.wr.rel[1])
 579         yield dut.wr.go.eq(0b10)
 580         yield
 581         addr = yield dut.addr_o
 582         print ("addr", addr)
 583         yield dut.wr.go.eq(0)
 584     else:
 585         addr = None
 586
 587     yield from wait_for(dut.wr.rel[0], test1st=True)
 588     yield dut.wr.go.eq(1)
 589     yield
 590     data = yield dut.data_o
 591     print (data)
 592     yield dut.wr.go.eq(0)
 593     yield from wait_for(dut.busy_o)
 594     yield
 595     # wait_for(dut.stwd_mem_o)
 596     return data, addr
 597
 598
 599 def scoreboard_sim(dut):
 600
 601     ###################
 602     # immediate version
 603
 604     # two STs (different addresses)
 605     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 606     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 607     yield
 608     # two LDs (deliberately LD from the 1st address then 2nd)
 609     data, addr = yield from load(dut, 4, 0, 2)
 610     assert data == 0x0003, "returned %x" % data
 611     data, addr  = yield from load(dut, 2, 0, 2)
 612     assert data == 0x0009, "returned %x" % data
 613     yield
 614
 615     # indexed version
 616     yield from store(dut, 4, 5, 3, 0, imm_ok=False)
 617     data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
 618     assert data == 0x0003, "returned %x" % data
 619
 620     # update-immediate version
 621     addr = yield from store(dut, 4, 6, 3, 2, update=True)
 622     assert addr == 0x0006, "returned %x" % addr
 623
 624     # update-indexed version
 625     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
 626     assert data == 0x0003, "returned %x" % data
 627     assert addr == 0x0009, "returned %x" % addr
 628
 629     # immediate *and* zero version
 630     data, addr  = yield from load(dut, 4, 5, 9, imm_ok=True, zero_a=True)
 631     assert data == 0x0003, "returned %x" % data
 632
 633
 634 class TestLDSTCompUnit(LDSTCompUnit):
 635
 636     def __init__(self, rwid):
 637         from soc.experiment.l0_cache import TstL0CacheBuffer
 638         self.l0 = l0 = TstL0CacheBuffer()
 639         pi = l0.l0.dports[0].pi
 640         LDSTCompUnit.__init__(self, pi, rwid, 4)
 641
 642     def elaborate(self, platform):
 643         m = LDSTCompUnit.elaborate(self, platform)
 644         m.submodules.l0 = self.l0
 645         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 646         return m
 647
 648
 649 def test_scoreboard():
 650
 651     dut = TestLDSTCompUnit(16)
 652     vl = rtlil.convert(dut, ports=dut.ports())
 653     with open("test_ldst_comp.il", "w") as f:
 654         f.write(vl)
 655
 656     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 657
 658
 659 class TestLDSTCompUnitRegSpec(LDSTCompUnit):
 660
 661     def __init__(self):
 662         from soc.experiment.l0_cache import TstL0CacheBuffer
 663         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 664         regspec = LDSTPipeSpec.regspec
 665         self.l0 = l0 = TstL0CacheBuffer()
 666         pi = l0.l0.dports[0].pi
 667         LDSTCompUnit.__init__(self, pi, regspec, 4)
 668
 669     def elaborate(self, platform):
 670         m = LDSTCompUnit.elaborate(self, platform)
 671         m.submodules.l0 = self.l0
 672         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 673         return m
 674
 675
 676 def test_scoreboard_regspec():
 677
 678     dut = TestLDSTCompUnitRegSpec()
 679     vl = rtlil.convert(dut, ports=dut.ports())
 680     with open("test_ldst_comp.il", "w") as f:
 681         f.write(vl)
 682
 683     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_regspec.vcd')
 684
 685
 686 if __name__ == '__main__':
 687     test_scoreboard_regspec()
 688     test_scoreboard()