src/soc/experiment/compldst_multi.py

   1 """ LOAD / STORE Computation Unit.
   2
   3     This module covers POWER9-compliant Load and Store operations,
   4     with selection on each between immediate and indexed mode as
   5     options for the calculation of the Effective Address (EA),
   6     and also "update" mode which optionally stores that EA into
   7     an additional register.
   8
   9     ----
  10     Note: it took 15 attempts over several weeks to redraw the diagram
  11     needed to capture this FSM properly.  To understand it fully, please
  12     take the time to review the links, video, and diagram.
  13     ----
  14
  15     Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
  16     compute the "Effective Address", and, when ready the operand (src3_i)
  17     is stored in the computed address (passed through to the PortInterface)
  18
  19     Loads are activated when Go_Write[0] is enabled.  The EA is computed,
  20     and (as long as there was no exception) the data comes out (at any
  21     time from the PortInterface), and is captured by the LDCompSTUnit.
  22
  23     Both LD and ST may request that the address be computed from summing
  24     operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
  25     the immediate (from the opcode).
  26
  27     Both LD and ST may also request "update" mode (op_is_update) which
  28     activates the use of Go_Write[1] to control storage of the EA into
  29     a *second* operand in the register file.
  30
  31     Thus this module has *TWO* write-requests to the register file and
  32     *THREE* read-requests to the register file (not all at the same time!)
  33     The regfile port usage is:
  34
  35     * LD-imm         1R1W
  36     * LD-imm-update  1R2W
  37     * LD-idx         2R1W
  38     * LD-idx-update  2R2W
  39
  40     * ST-imm         2R
  41     * ST-imm-update  2R1W
  42     * ST-idx         3R
  43     * ST-idx-update  3R1W
  44
  45     It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
  46     is not suited to (nmigen.FSM is clock-driven, and some aspects of
  47     the nested FSMs below are *combinatorial*).
  48
  49     * One FSM covers Operand collection and communication address-side
  50       with the LD/ST PortInterface.  its role ends when "RD_DONE" is asserted
  51
  52     * A second FSM activates to cover LD.  it activates if op_is_ld is true
  53
  54     * A third FSM activates to cover ST.  it activates if op_is_st is true
  55
  56     * The "overall" (fourth) FSM coordinates the progression and completion
  57       of the three other FSMs, firing "WR_RESET" which switches off "busy"
  58
  59     Full diagram:
  60     https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
  61
  62     Links including to walk-through videos:
  63     * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
  64     * http://libre-soc.org/openpower/isa/fixedload
  65     * http://libre-soc.org/openpower/isa/fixedstore
  66
  67     Related Bugreports:
  68     * https://bugs.libre-soc.org/show_bug.cgi?id=302
  69
  70     Terminology:
  71
  72     * EA - Effective Address
  73     * LD - Load
  74     * ST - Store
  75 """
  76
  77 from nmigen.compat.sim import run_simulation
  78 from nmigen.cli import verilog, rtlil
  79 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
  80 from nmigen.hdl.rec import Record, Layout
  81
  82 from nmutil.latch import SRLatch, latchregister
  83
  84 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  85 from soc.experiment.l0_cache import PortInterface
  86 from soc.experiment.testmem import TestMemory
  87
  88 from soc.decoder.power_enums import InternalOp, Function
  89 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  90
  91
  92 class LDSTCompUnitRecord(CompUnitRecord):
  93     def __init__(self, rwid, name=None):
  94         CompUnitRecord.__init__(self, CompLDSTOpSubset, rwid,
  95                                 n_src=3, n_dst=2, name=name)
  96
  97         self.ad = go_record(1, name="ad") # address go in, req out
  98         self.st = go_record(1, name="st") # store go in, req out
  99
 100         self.addr_exc_o = Signal(reset_less=True)   # address exception
 101
 102         self.ld_o = Signal(reset_less=True)  # operation is a LD
 103         self.st_o = Signal(reset_less=True)  # operation is a ST
 104
 105         # hmm... are these necessary?
 106         self.load_mem_o = Signal(reset_less=True)  # activate memory LOAD
 107         self.stwd_mem_o = Signal(reset_less=True)  # activate memory STORE
 108
 109
 110 class LDSTCompUnit(Elaboratable):
 111     """LOAD / STORE Computation Unit
 112
 113     Inputs
 114     ------
 115
 116     * :pi:     a PortInterface to the memory subsystem (read-write capable)
 117     * :rwid:   register width
 118     * :awid:   address width
 119
 120     Data inputs
 121     -----------
 122     * :src_i:  Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
 123
 124     Data (outputs)
 125     --------------
 126     * :data_o:     Dest out (LD)          - managed by wr[0] go/req
 127     * :addr_o:     Address out (LD or ST) - managed by wr[1] go/req
 128     * :addr_exc_o: Address/Data Exception occurred.  LD/ST must terminate
 129
 130     TODO: make addr_exc_o a data-type rather than a single-bit signal
 131           (see bug #302)
 132
 133     Control Signals (In)
 134     --------------------
 135
 136     * :oper_i:     operation being carried out (POWER9 decode LD/ST subset)
 137     * :issue_i:    LD/ST is being "issued".
 138     * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
 139     * :go_rd_i:    read is being actioned (latches in src regs)
 140     * :go_wr_i:    write mode (exactly like ALU CompUnit)
 141     * :go_ad_i:    address is being actioned (triggers actual mem LD)
 142     * :go_st_i:    store is being actioned (triggers actual mem STORE)
 143     * :go_die_i:   resets the unit back to "wait for issue"
 144
 145     Control Signals (Out)
 146     ---------------------
 147
 148     * :busy_o:      function unit is busy
 149     * :rd_rel_o:    request src1/src2
 150     * :adr_rel_o:   request address (from mem)
 151     * :sto_rel_o:   request store (to mem)
 152     * :req_rel_o:   request write (result)
 153     * :load_mem_o:  activate memory LOAD
 154     * :stwd_mem_o:  activate memory STORE
 155
 156     Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
 157     in a single cycle and the CompUnit set back to doing another op.
 158     This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
 159     depending on whether the operation is a ST or LD.
 160     """
 161
 162     def __init__(self, pi, rwid=64, awid=48, debugtest=False):
 163         self.rwid = rwid
 164         self.awid = awid
 165         self.pi = pi
 166         self.cu = cu = LDSTCompUnitRecord(rwid)
 167         self.debugtest = debugtest
 168
 169         # POWER-compliant LD/ST has index and update: *fixed* number of ports
 170         self.n_src = n_src = 3   # RA, RB, RT/RS
 171         self.n_dst = n_dst = 2 # RA, RT/RS
 172
 173         # set up array of src and dest signals
 174         for i in range(n_src):
 175             j = i + 1 # name numbering to match src1/src2
 176             name = "src%d_i" % j
 177             setattr(self, name, getattr(cu, name))
 178
 179         dst = []
 180         for i in range(n_dst):
 181             j = i + 1 # name numbering to match dest1/2...
 182             name = "dest%d_i" % j
 183             setattr(self, name, getattr(cu, name))
 184
 185         # convenience names
 186         self.rd = cu.rd
 187         self.wr = cu.wr
 188         self.ad = cu.ad
 189         self.st = cu.st
 190
 191         self.go_rd_i = self.rd.go # temporary naming
 192         self.go_wr_i = self.wr.go # temporary naming
 193         self.go_ad_i = self.ad.go # temp naming: go address in
 194         self.go_st_i = self.st.go  # temp naming: go store in
 195
 196         self.rd_rel_o = self.rd.rel # temporary naming
 197         self.req_rel_o = self.wr.rel # temporary naming
 198         self.adr_rel_o = self.ad.rel  # request address (from mem)
 199         self.sto_rel_o = self.st.rel  # request store (to mem)
 200
 201         self.issue_i = cu.issue_i
 202         self.shadown_i = cu.shadown_i
 203         self.go_die_i = cu.go_die_i
 204
 205         self.oper_i = cu.oper_i
 206         self.src_i = cu._src_i
 207         self.dest = cu._dest
 208
 209         self.data_o = self.dest[0]  # Dest1 out: RT
 210         self.addr_o = self.dest[1]  # Address out (LD or ST) - Update => RA
 211         self.addr_exc_o = cu.addr_exc_o
 212         self.done_o = cu.done_o
 213         self.busy_o = cu.busy_o
 214
 215         self.ld_o = cu.ld_o
 216         self.st_o = cu.st_o
 217
 218         self.load_mem_o = cu.load_mem_o
 219         self.stwd_mem_o = cu.stwd_mem_o
 220
 221     def elaborate(self, platform):
 222         m = Module()
 223
 224         # temp/convenience
 225         comb = m.d.comb
 226         sync = m.d.sync
 227         issue_i = self.issue_i
 228
 229         #####################
 230         # latches for the FSM.
 231         m.submodules.opc_l = opc_l = SRLatch(sync=False, name="opc")
 232         m.submodules.src_l = src_l = SRLatch(False, self.n_src, name="src")
 233         m.submodules.alu_l = alu_l = SRLatch(sync=False, name="alu")
 234         m.submodules.adr_l = adr_l = SRLatch(sync=False, name="adr")
 235         m.submodules.lod_l = lod_l = SRLatch(sync=False, name="lod")
 236         m.submodules.sto_l = sto_l = SRLatch(sync=False, name="sto")
 237         m.submodules.wri_l = wri_l = SRLatch(sync=False, name="wri")
 238         m.submodules.upd_l = upd_l = SRLatch(sync=False, name="upd")
 239         m.submodules.rst_l = rst_l = SRLatch(sync=False, name="rst")
 240
 241         ####################
 242         # signals
 243
 244         # opcode decode
 245         op_is_ld = Signal(reset_less=True)
 246         op_is_st = Signal(reset_less=True)
 247
 248         # ALU/LD data output control
 249         alu_valid = Signal(reset_less=True) # ALU operands are valid
 250         alu_ok = Signal(reset_less=True)    # ALU out ok (1 clock delay valid)
 251         addr_ok = Signal(reset_less=True)   # addr ok (from PortInterface)
 252         ld_ok = Signal(reset_less=True)     # LD out ok from PortInterface
 253         wr_any = Signal(reset_less=True)    # any write (incl. store)
 254         rda_any = Signal(reset_less=True)   # any read for address ops
 255         rd_done = Signal(reset_less=True)   # all *necessary* operands read
 256         wr_reset = Signal(reset_less=True)  # final reset condition
 257
 258         # LD and ALU out
 259         alu_o = Signal(self.rwid, reset_less=True)
 260         ldd_o = Signal(self.rwid, reset_less=True)
 261
 262         # XXX TODO ZEROing just lije in ComUnit
 263
 264         # select immediate or src2 reg to add
 265         src2_or_imm = Signal(self.rwid, reset_less=True)
 266         src_sel = Signal(reset_less=True)
 267
 268         ##############################
 269         # reset conditions for latches
 270
 271         # temporaries (also convenient when debugging)
 272         reset_o = Signal(reset_less=True)             # reset opcode
 273         reset_w = Signal(reset_less=True)             # reset write
 274         reset_u = Signal(reset_less=True)             # reset update
 275         reset_a = Signal(reset_less=True)             # reset adr latch
 276         reset_i = Signal(reset_less=True)             # issue|die (use a lot)
 277         reset_r = Signal(self.n_src, reset_less=True) # reset src
 278         reset_s = Signal(reset_less=True)             # reset store
 279
 280         comb += reset_i.eq(issue_i | self.go_die_i)       # various
 281         comb += reset_o.eq(wr_reset | self.go_die_i)      # opcode reset
 282         comb += reset_w.eq(self.wr.go[0] | self.go_die_i) # write reg 1
 283         comb += reset_u.eq(self.wr.go[1] | self.go_die_i) # update (reg 2)
 284         comb += reset_s.eq(self.go_st_i | self.go_die_i)  # store reset
 285         comb += reset_r.eq(self.rd.go | Repl(self.go_die_i, self.n_src))
 286         comb += reset_a.eq(self.go_ad_i | self.go_die_i)
 287
 288         ##########################
 289         # FSM implemented through sequence of latches.  approximately this:
 290         # - opc_l       : opcode
 291         #    - src_l[0] : operands
 292         #    - src_l[1]
 293         #       - alu_l : looks after add of src1/2/imm (EA)
 294         #       - adr_l : waits for add (EA)
 295         #       - upd_l : waits for adr and Regfile (port 2)
 296         #    - src_l[2] : ST
 297         # - lod_l       : waits for adr (EA) and for LD Data
 298         # - wri_l       : waits for LD Data and Regfile (port 1)
 299         # - st_l        : waits for alu and operand2
 300         # - rst_l       : waits for all FSM paths to converge.
 301         # NOTE: use sync to stop combinatorial loops.
 302
 303         # opcode latch - inverted so that busy resets to 0
 304         # note this MUST be sync so as to avoid a combinatorial loop
 305         # between busy_o and issue_i on the reset latch (rst_l)
 306         sync += opc_l.s.eq(issue_i)  # XXX NOTE: INVERTED FROM book!
 307         sync += opc_l.r.eq(reset_o)  # XXX NOTE: INVERTED FROM book!
 308
 309         # src operand latch
 310         sync += src_l.s.eq(Repl(issue_i, self.n_src))
 311         sync += src_l.r.eq(reset_r)
 312
 313         # alu latch.  use sync-delay between alu_ok and valid to generate pulse
 314         comb += alu_l.s.eq(reset_i)
 315         comb += alu_l.r.eq(alu_ok & ~alu_valid & ~rda_any)
 316
 317         # addr latch
 318         comb += adr_l.s.eq(reset_i)
 319         sync += adr_l.r.eq(reset_a)
 320
 321         # ld latch
 322         comb += lod_l.s.eq(reset_i)
 323         comb += lod_l.r.eq(ld_ok)
 324
 325         # dest operand latch
 326         comb += wri_l.s.eq(issue_i)
 327         sync += wri_l.r.eq(reset_w)
 328
 329         # update-mode operand latch (EA written to reg 2)
 330         sync += upd_l.s.eq(reset_i)
 331         sync += upd_l.r.eq(reset_u)
 332
 333         # store latch
 334         comb += sto_l.s.eq(addr_ok & op_is_st)
 335         comb += sto_l.r.eq(reset_s)
 336
 337         # reset latch
 338         comb += rst_l.s.eq(addr_ok) # start when address is ready
 339         comb += rst_l.r.eq(issue_i)
 340
 341         # create a latch/register for the operand
 342         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
 343         latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 344
 345         # and for LD
 346         ldd_r = Signal(self.rwid, reset_less=True)  # Dest register
 347         latchregister(m, ldd_o, ldd_r, ld_ok, name="ldo_r")
 348
 349         # and for each input from the incoming src operands
 350         srl = []
 351         for i in range(self.n_src):
 352             name = "src_r%d" % i
 353             src_r = Signal(self.rwid, name=name, reset_less=True)
 354             latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
 355             srl.append(src_r)
 356
 357         # and one for the output from the ADD (for the EA)
 358         addr_r = Signal(self.rwid, reset_less=True)  # Effective Address Latch
 359         latchregister(m, alu_o, addr_r, alu_l.q, "ea_r")
 360
 361         # select either immediate or src2 if opcode says so
 362         op_is_imm = oper_r.imm_data.imm_ok
 363         src2_or_imm = Signal(self.rwid, reset_less=True)
 364         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, oper_r.imm_data.imm, srl[1]))
 365
 366         # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
 367         sync += alu_o.eq(srl[0] + src2_or_imm) # actual EA
 368         sync += alu_ok.eq(alu_valid)             # keep ack in sync with EA
 369
 370         # decode bits of operand (latched)
 371         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
 372         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
 373         op_is_update = oper_r.update                                 # UPDATE
 374         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 375         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 376         comb += self.ld_o.eq(op_is_ld)
 377         comb += self.st_o.eq(op_is_st)
 378
 379         ############################
 380         # Control Signal calculation
 381
 382         # busy signal
 383         busy_o = self.busy_o
 384         comb += self.busy_o.eq(opc_l.q) # | self.pi.busy_o)  # busy out
 385
 386         # 1st operand read-request is simple: always need it
 387         comb += self.rd.rel[0].eq(src_l.q[0] & busy_o)
 388
 389         # 2nd operand only needed when immediate is not active
 390         comb += self.rd.rel[1].eq(src_l.q[1] & busy_o & ~op_is_imm)
 391
 392         # note when the address-related read "go" signals are active
 393         comb += rda_any.eq(self.rd.go[0] | self.rd.go[1])
 394
 395         # alu input valid when 1st and 2nd ops done (or imm not active)
 396         comb += alu_valid.eq(busy_o & ~(self.rd.rel[0] | self.rd.rel[1]))
 397
 398         # 3rd operand only needed when operation is a store
 399         comb += self.rd.rel[2].eq(src_l.q[2] & busy_o & op_is_st)
 400
 401         # all reads done when alu is valid and 3rd operand needed
 402         comb += rd_done.eq(alu_valid & ~self.rd.rel[2])
 403
 404         # address release only if addr ready, but Port must be idle
 405         comb += self.adr_rel_o.eq(adr_l.q & busy_o)
 406
 407         # store release when st ready *and* all operands read (and no shadow)
 408         comb += self.st.rel.eq(sto_l.q & busy_o & rd_done & op_is_st &
 409                                self.shadown_i)
 410
 411         # request write of LD result.  waits until shadow is dropped.
 412         comb += self.wr.rel[0].eq(wri_l.q & busy_o & lod_l.qn & op_is_ld &
 413                                   self.shadown_i)
 414
 415         # request write of EA result only in update mode
 416         comb += self.wr.rel[1].eq(upd_l.q & busy_o & op_is_update &
 417                                   self.shadown_i)
 418
 419         # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
 420         comb += wr_any.eq(self.st.go | self.wr.go[0] | self.wr.go[1])
 421         comb += wr_reset.eq(rst_l.q & busy_o & self.shadown_i &
 422                     ~(self.st.rel | self.wr.rel[0] | self.wr.rel[1]) &
 423                      (lod_l.qn | op_is_st))
 424         comb += self.done_o.eq(wr_reset)
 425
 426         ######################
 427         # Data/Address outputs
 428
 429         # put the LD-output register directly onto the output bus on a go_write
 430         with m.If(self.wr.go[0]):
 431             comb += self.data_o.eq(ldd_r)
 432
 433         # "update" mode, put address out on 2nd go-write
 434         with m.If(op_is_update & self.wr.go[1]):
 435             comb += self.addr_o.eq(addr_r)
 436
 437         ###########################
 438         # PortInterface connections
 439         pi = self.pi
 440
 441         # connect to LD/ST PortInterface.
 442         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
 443         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
 444         comb += pi.op.eq(self.oper_i)    # op details (not all needed)
 445         # address
 446         comb += pi.addr.data.eq(addr_r)           # EA from adder
 447         comb += pi.addr.ok.eq(alu_ok & lod_l.q) # "go do address stuff"
 448         comb += self.addr_exc_o.eq(pi.addr_exc_o) # exception occurred
 449         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 450         # ld - ld gets latched in via lod_l
 451         comb += ldd_o.eq(pi.ld.data)  # ld data goes into ld reg (above)
 452         comb += ld_ok.eq(pi.ld.ok) # ld.ok *closes* (freezes) ld data
 453         # store - data goes in based on go_st
 454         comb += pi.st.data.eq(srl[2]) # 3rd operand latch
 455         comb += pi.st.ok.eq(self.st.go)  # go store signals st data valid
 456
 457         return m
 458
 459     def __iter__(self):
 460         yield self.rd.go
 461         yield self.go_ad_i
 462         yield self.wr.go
 463         yield self.go_st_i
 464         yield self.issue_i
 465         yield self.shadown_i
 466         yield self.go_die_i
 467         yield from self.oper_i.ports()
 468         yield from self.src_i
 469         yield self.busy_o
 470         yield self.rd.rel
 471         yield self.adr_rel_o
 472         yield self.sto_rel_o
 473         yield self.wr.rel
 474         yield self.data_o
 475         yield self.addr_o
 476         yield self.load_mem_o
 477         yield self.stwd_mem_o
 478
 479     def ports(self):
 480         return list(self)
 481
 482
 483 def wait_for(sig, wait=True, test1st=False):
 484     v = (yield sig)
 485     print("wait for", sig, v, wait, test1st)
 486     if test1st and bool(v) == wait:
 487         return
 488     while True:
 489         yield
 490         v = (yield sig)
 491         #print("...wait for", sig, v)
 492         if bool(v) == wait:
 493             break
 494
 495
 496 def store(dut, src1, src2, src3, imm, imm_ok=True, update=False):
 497     print ("ST", src1, src2, src3, imm, imm_ok, update)
 498     yield dut.oper_i.insn_type.eq(InternalOp.OP_STORE)
 499     yield dut.src1_i.eq(src1)
 500     yield dut.src2_i.eq(src2)
 501     yield dut.src3_i.eq(src3)
 502     yield dut.oper_i.imm_data.imm.eq(imm)
 503     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 504     yield dut.oper_i.update.eq(update)
 505     yield dut.issue_i.eq(1)
 506     yield
 507     yield dut.issue_i.eq(0)
 508     yield
 509     if imm_ok:
 510         yield dut.rd.go.eq(0b101)
 511     else:
 512         yield dut.rd.go.eq(0b111)
 513     yield from wait_for(dut.rd.rel)
 514     yield dut.rd.go.eq(0)
 515
 516     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 517     #yield from wait_for(dut.adr_rel_o)
 518     #yield dut.ad.go.eq(1)
 519     #yield
 520     #yield dut.ad.go.eq(0)
 521
 522     if update:
 523         yield from wait_for(dut.wr.rel[1])
 524         yield dut.wr.go.eq(0b10)
 525         yield
 526         addr = yield dut.addr_o
 527         print ("addr", addr)
 528         yield dut.wr.go.eq(0)
 529     else:
 530         addr = None
 531
 532     yield from wait_for(dut.sto_rel_o)
 533     yield dut.go_st_i.eq(1)
 534     yield
 535     yield dut.go_st_i.eq(0)
 536     yield from wait_for(dut.busy_o, False)
 537     #wait_for(dut.stwd_mem_o)
 538     yield
 539     return addr
 540
 541
 542 def load(dut, src1, src2, imm, imm_ok=True, update=False):
 543     print ("LD", src1, src2, imm, imm_ok, update)
 544     yield dut.oper_i.insn_type.eq(InternalOp.OP_LOAD)
 545     yield dut.src1_i.eq(src1)
 546     yield dut.src2_i.eq(src2)
 547     yield dut.oper_i.imm_data.imm.eq(imm)
 548     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
 549     yield dut.issue_i.eq(1)
 550     yield
 551     yield dut.issue_i.eq(0)
 552     yield
 553     if imm_ok:
 554         yield dut.rd.go.eq(0b01)
 555     else:
 556         yield dut.rd.go.eq(0b11)
 557     yield from wait_for(dut.rd.rel)
 558     yield dut.rd.go.eq(0)
 559
 560     yield from wait_for(dut.adr_rel_o, False, test1st=True)
 561     #yield dut.ad.go.eq(1)
 562     #yield
 563     #yield dut.ad.go.eq(0)
 564
 565     if update:
 566         yield from wait_for(dut.wr.rel[1])
 567         yield dut.wr.go.eq(0b10)
 568         yield
 569         addr = yield dut.addr_o
 570         print ("addr", addr)
 571         yield dut.wr.go.eq(0)
 572     else:
 573         addr = None
 574
 575     yield from wait_for(dut.wr.rel[0], test1st=True)
 576     yield dut.wr.go.eq(1)
 577     yield
 578     data = yield dut.data_o
 579     print (data)
 580     yield dut.wr.go.eq(0)
 581     yield from wait_for(dut.busy_o)
 582     yield
 583     # wait_for(dut.stwd_mem_o)
 584     return data, addr
 585
 586
 587 def scoreboard_sim(dut):
 588
 589     ###################
 590     # immediate version
 591
 592     # two STs (different addresses)
 593     yield from store(dut, 4, 0, 3, 2)  # ST reg4 into addr rfile[reg3]+2
 594     yield from store(dut, 2, 0, 9, 2)  # ST reg4 into addr rfile[reg9]+2
 595     yield
 596     # two LDs (deliberately LD from the 1st address then 2nd)
 597     data, addr = yield from load(dut, 4, 0, 2)
 598     assert data == 0x0003, "returned %x" % data
 599     data, addr  = yield from load(dut, 2, 0, 2)
 600     assert data == 0x0009, "returned %x" % data
 601     yield
 602
 603     # indexed version
 604     yield from store(dut, 4, 5, 3, 0, imm_ok=False)
 605     data, addr = yield from load(dut, 4, 5, 0, imm_ok=False)
 606     assert data == 0x0003, "returned %x" % data
 607
 608     # update-immediate version
 609     addr = yield from store(dut, 4, 6, 3, 2, update=True)
 610     assert addr == 0x0006, "returned %x" % addr
 611
 612     # update-indexed version
 613     data, addr  = yield from load(dut, 4, 5, 0, imm_ok=False, update=True)
 614     assert addr == 0x0009, "returned %x" % addr
 615
 616 class TestLDSTCompUnit(LDSTCompUnit):
 617
 618     def __init__(self, rwid):
 619         from soc.experiment.l0_cache import TstL0CacheBuffer
 620         self.l0 = l0 = TstL0CacheBuffer()
 621         pi = l0.l0.dports[0].pi
 622         LDSTCompUnit.__init__(self, pi, rwid, 4)
 623
 624     def elaborate(self, platform):
 625         m = LDSTCompUnit.elaborate(self, platform)
 626         m.submodules.l0 = self.l0
 627         m.d.comb += self.ad.go.eq(self.ad.rel) # link addr-go direct to rel
 628         return m
 629
 630
 631 def test_scoreboard():
 632
 633     dut = TestLDSTCompUnit(16)
 634     vl = rtlil.convert(dut, ports=dut.ports())
 635     with open("test_ldst_comp.il", "w") as f:
 636         f.write(vl)
 637
 638     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 639
 640
 641 if __name__ == '__main__':
 642     test_scoreboard()