1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
87 from nmutil
.byterev
import byte_reverse
89 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
90 from soc
.experiment
.l0_cache
import PortInterface
91 from soc
.fu
.regspec
import RegSpecAPI
93 from soc
.decoder
.power_enums
import InternalOp
, Function
94 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
95 from soc
.decoder
.power_decoder2
import Data
98 class LDSTCompUnitRecord(CompUnitRecord
):
99 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
100 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
101 n_src
=3, n_dst
=2, name
=name
)
103 self
.ad
= go_record(1, name
="ad") # address go in, req out
104 self
.st
= go_record(1, name
="st") # store go in, req out
106 self
.addr_exc_o
= Signal(reset_less
=True) # address exception
108 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
109 self
.st_o
= Signal(reset_less
=True) # operation is a ST
111 # hmm... are these necessary?
112 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
113 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
116 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
117 """LOAD / STORE Computation Unit
122 * :pi: a PortInterface to the memory subsystem (read-write capable)
123 * :rwid: register width
124 * :awid: address width
128 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
132 * :data_o: Dest out (LD) - managed by wr[0] go/req
133 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
134 * :addr_exc_o: Address/Data Exception occurred. LD/ST must terminate
136 TODO: make addr_exc_o a data-type rather than a single-bit signal
142 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
143 * :issue_i: LD/ST is being "issued".
144 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
145 * :go_rd_i: read is being actioned (latches in src regs)
146 * :go_wr_i: write mode (exactly like ALU CompUnit)
147 * :go_ad_i: address is being actioned (triggers actual mem LD)
148 * :go_st_i: store is being actioned (triggers actual mem STORE)
149 * :go_die_i: resets the unit back to "wait for issue"
151 Control Signals (Out)
152 ---------------------
154 * :busy_o: function unit is busy
155 * :rd_rel_o: request src1/src2
156 * :adr_rel_o: request address (from mem)
157 * :sto_rel_o: request store (to mem)
158 * :req_rel_o: request write (result)
159 * :load_mem_o: activate memory LOAD
160 * :stwd_mem_o: activate memory STORE
162 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
163 in a single cycle and the CompUnit set back to doing another op.
164 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
165 depending on whether the operation is a ST or LD.
167 Note: LDSTCompUnit takes care of LE/BE normalisation:
168 * LD data is normalised after receipt from the PortInterface
169 * ST data is normalised *prior* to sending onto the PortInterface
170 TODO: use one module for the byte-reverse as it's quite expensive in gates
173 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
175 super().__init
__(rwid
)
178 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
)
179 self
.debugtest
= debugtest
181 # POWER-compliant LD/ST has index and update: *fixed* number of ports
182 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
183 self
.n_dst
= n_dst
= 2 # RA, RT/RS
185 # set up array of src and dest signals
186 for i
in range(n_src
):
187 j
= i
+ 1 # name numbering to match src1/src2
189 setattr(self
, name
, getattr(cu
, name
))
192 for i
in range(n_dst
):
193 j
= i
+ 1 # name numbering to match dest1/2...
194 name
= "dest%d_o" % j
195 setattr(self
, name
, getattr(cu
, name
))
200 self
.rdmaskn
= cu
.rdmaskn
201 self
.wrmask
= cu
.wrmask
206 # HACK: get data width from dest[0]. this is used across the board
207 # (it really shouldn't be)
208 self
.data_wid
= self
.dest
[0].shape()
210 self
.go_rd_i
= self
.rd
.go
# temporary naming
211 self
.go_wr_i
= self
.wr
.go
# temporary naming
212 self
.go_ad_i
= self
.ad
.go
# temp naming: go address in
213 self
.go_st_i
= self
.st
.go
# temp naming: go store in
215 self
.rd_rel_o
= self
.rd
.rel
# temporary naming
216 self
.req_rel_o
= self
.wr
.rel
# temporary naming
217 self
.adr_rel_o
= self
.ad
.rel
# request address (from mem)
218 self
.sto_rel_o
= self
.st
.rel
# request store (to mem)
220 self
.issue_i
= cu
.issue_i
221 self
.shadown_i
= cu
.shadown_i
222 self
.go_die_i
= cu
.go_die_i
224 self
.oper_i
= cu
.oper_i
225 self
.src_i
= cu
._src
_i
227 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
228 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
229 self
.addr_exc_o
= cu
.addr_exc_o
230 self
.done_o
= cu
.done_o
231 self
.busy_o
= cu
.busy_o
236 self
.load_mem_o
= cu
.load_mem_o
237 self
.stwd_mem_o
= cu
.stwd_mem_o
239 def elaborate(self
, platform
):
245 issue_i
= self
.issue_i
247 #####################
248 # latches for the FSM.
249 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
250 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
251 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
252 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
253 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
254 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
255 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
256 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
257 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
263 op_is_ld
= Signal(reset_less
=True)
264 op_is_st
= Signal(reset_less
=True)
266 # ALU/LD data output control
267 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
268 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
269 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
270 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
271 wr_any
= Signal(reset_less
=True) # any write (incl. store)
272 rda_any
= Signal(reset_less
=True) # any read for address ops
273 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
274 wr_reset
= Signal(reset_less
=True) # final reset condition
277 alu_o
= Signal(self
.data_wid
, reset_less
=True)
278 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
280 ##############################
281 # reset conditions for latches
283 # temporaries (also convenient when debugging)
284 reset_o
= Signal(reset_less
=True) # reset opcode
285 reset_w
= Signal(reset_less
=True) # reset write
286 reset_u
= Signal(reset_less
=True) # reset update
287 reset_a
= Signal(reset_less
=True) # reset adr latch
288 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
289 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
290 reset_s
= Signal(reset_less
=True) # reset store
292 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
293 comb
+= reset_o
.eq(wr_reset | self
.go_die_i
) # opcode reset
294 comb
+= reset_w
.eq(self
.wr
.go
[0] | self
.go_die_i
) # write reg 1
295 comb
+= reset_u
.eq(self
.wr
.go
[1] | self
.go_die_i
) # update (reg 2)
296 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
297 comb
+= reset_r
.eq(self
.rd
.go |
Repl(self
.go_die_i
, self
.n_src
))
298 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
300 p_st_go
= Signal(reset_less
=True)
301 sync
+= p_st_go
.eq(self
.st
.go
)
303 ##########################
304 # FSM implemented through sequence of latches. approximately this:
306 # - src_l[0] : operands
308 # - alu_l : looks after add of src1/2/imm (EA)
309 # - adr_l : waits for add (EA)
310 # - upd_l : waits for adr and Regfile (port 2)
312 # - lod_l : waits for adr (EA) and for LD Data
313 # - wri_l : waits for LD Data and Regfile (port 1)
314 # - st_l : waits for alu and operand2
315 # - rst_l : waits for all FSM paths to converge.
316 # NOTE: use sync to stop combinatorial loops.
318 # opcode latch - inverted so that busy resets to 0
319 # note this MUST be sync so as to avoid a combinatorial loop
320 # between busy_o and issue_i on the reset latch (rst_l)
321 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
322 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
325 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
326 sync
+= src_l
.r
.eq(reset_r
)
328 # alu latch. use sync-delay between alu_ok and valid to generate pulse
329 comb
+= alu_l
.s
.eq(reset_i
)
330 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
333 comb
+= adr_l
.s
.eq(reset_i
)
334 sync
+= adr_l
.r
.eq(reset_a
)
337 comb
+= lod_l
.s
.eq(reset_i
)
338 comb
+= lod_l
.r
.eq(ld_ok
)
341 comb
+= wri_l
.s
.eq(issue_i
)
342 sync
+= wri_l
.r
.eq(reset_w |
Repl(self
.done_o
, self
.n_dst
))
344 # update-mode operand latch (EA written to reg 2)
345 sync
+= upd_l
.s
.eq(reset_i
)
346 sync
+= upd_l
.r
.eq(reset_u
)
349 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
350 comb
+= sto_l
.r
.eq(reset_s | p_st_go
)
353 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
354 comb
+= rst_l
.r
.eq(issue_i
)
356 # create a latch/register for the operand
357 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
358 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, name
="oper_l")
361 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
362 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
364 # and for each input from the incoming src operands
366 for i
in range(self
.n_src
):
368 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
369 latchregister(m
, self
.src_i
[i
], src_r
, src_l
.q
[i
], name
+ '_l')
372 # and one for the output from the ADD (for the EA)
373 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
374 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
376 # select either zero or src1 if opcode says so
377 op_is_z
= oper_r
.zero_a
378 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
379 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
381 # select either immediate or src2 if opcode says so
382 op_is_imm
= oper_r
.imm_data
.imm_ok
383 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
384 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
, srl
[1]))
386 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
387 sync
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
388 sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
390 # decode bits of operand (latched)
391 comb
+= op_is_st
.eq(oper_r
.insn_type
== InternalOp
.OP_STORE
) # ST
392 comb
+= op_is_ld
.eq(oper_r
.insn_type
== InternalOp
.OP_LOAD
) # LD
393 op_is_update
= oper_r
.update
# UPDATE
394 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
395 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
396 comb
+= self
.ld_o
.eq(op_is_ld
)
397 comb
+= self
.st_o
.eq(op_is_st
)
399 ############################
400 # Control Signal calculation
404 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
406 # 1st operand read-request only when zero not active
407 # 2nd operand only needed when immediate is not active
408 slg
= Cat(op_is_z
, op_is_imm
)
409 bro
= Repl(self
.busy_o
, self
.n_src
)
410 comb
+= self
.rd
.rel
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
412 # note when the address-related read "go" signals are active
413 comb
+= rda_any
.eq(self
.rd
.go
[0] | self
.rd
.go
[1])
415 # alu input valid when 1st and 2nd ops done (or imm not active)
416 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel
[0] | self
.rd
.rel
[1]))
418 # 3rd operand only needed when operation is a store
419 comb
+= self
.rd
.rel
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
421 # all reads done when alu is valid and 3rd operand needed
422 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel
[2])
424 # address release only if addr ready, but Port must be idle
425 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
427 # store release when st ready *and* all operands read (and no shadow)
428 comb
+= self
.st
.rel
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
431 # request write of LD result. waits until shadow is dropped.
432 comb
+= self
.wr
.rel
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
433 op_is_ld
& self
.shadown_i
)
435 # request write of EA result only in update mode
436 comb
+= self
.wr
.rel
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
439 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
440 comb
+= wr_any
.eq(self
.st
.go | p_st_go | self
.wr
.go
[0] | self
.wr
.go
[1])
441 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
&
442 ~
(self
.st
.rel | self
.wr
.rel
[0] | self
.wr
.rel
[1]) &
443 (lod_l
.qn | op_is_st
))
444 comb
+= self
.done_o
.eq(wr_reset
)
446 ######################
447 # Data/Address outputs
449 # put the LD-output register directly onto the output bus on a go_write
450 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
451 with m
.If(self
.wr
.go
[0]):
452 comb
+= self
.dest
[0].eq(ldd_r
)
454 # "update" mode, put address out on 2nd go-write
455 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
456 with m
.If(op_is_update
& self
.wr
.go
[1]):
457 comb
+= self
.dest
[1].eq(addr_r
)
459 # need to look like MultiCompUnit: put wrmask out.
460 # XXX may need to make this enable only when write active
461 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
463 ###########################
464 # PortInterface connections
467 # connect to LD/ST PortInterface.
468 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
469 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
470 comb
+= pi
.data_len
.eq(self
.oper_i
.data_len
) # data_len
472 comb
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
473 comb
+= pi
.addr
.ok
.eq(alu_ok
& (lod_l
.q | sto_l
.q
)) # "do address stuff"
474 comb
+= self
.addr_exc_o
.eq(pi
.addr_exc_o
) # exception occurred
475 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
477 # byte-reverse on LD - yes this is inverted
478 with m
.If(self
.oper_i
.byte_reverse
):
479 comb
+= ldd_o
.eq(pi
.ld
.data
) # put data out, straight (as BE)
481 # byte-reverse the data based on ld/st width (turn it to LE)
482 data_len
= self
.oper_i
.data_len
483 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
484 comb
+= ldd_o
.eq(lddata_r
) # put reversed- data out
485 # ld - ld gets latched in via lod_l
486 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
488 # yes this also looks odd (inverted)
489 with m
.If(self
.oper_i
.byte_reverse
):
490 comb
+= pi
.st
.data
.eq(srl
[2]) # 3rd operand latch
492 # byte-reverse the data based on width
493 data_len
= self
.oper_i
.data_len
494 stdata_r
= byte_reverse(m
, 'stdata_r', srl
[2], data_len
)
495 comb
+= pi
.st
.data
.eq(stdata_r
)
496 # store - data goes in based on go_st
497 comb
+= pi
.st
.ok
.eq(self
.st
.go
) # go store signals st data valid
501 def get_out(self
, i
):
502 """make LDSTCompUnit look like RegSpecALUAPI"""
517 yield from self
.oper_i
.ports()
518 yield from self
.src_i
524 yield from self
.data_o
.ports()
525 yield from self
.addr_o
.ports()
526 yield self
.load_mem_o
527 yield self
.stwd_mem_o
533 def wait_for(sig
, wait
=True, test1st
=False):
535 print("wait for", sig
, v
, wait
, test1st
)
536 if test1st
and bool(v
) == wait
:
541 #print("...wait for", sig, v)
546 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
548 print ("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
549 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_STORE
)
550 yield dut
.oper_i
.data_len
.eq(2) # half-word
551 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
552 yield dut
.src1_i
.eq(src1
)
553 yield dut
.src2_i
.eq(src2
)
554 yield dut
.src3_i
.eq(src3
)
555 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
556 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
557 yield dut
.oper_i
.update
.eq(update
)
558 yield dut
.issue_i
.eq(1)
560 yield dut
.issue_i
.eq(0)
566 # wait for all active rel signals to come up
568 rel
= yield dut
.rd
.rel
569 if rel
== active_rel
:
572 yield dut
.rd
.go
.eq(active_rel
)
574 yield dut
.rd
.go
.eq(0)
576 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
577 #yield from wait_for(dut.adr_rel_o)
578 #yield dut.ad.go.eq(1)
580 #yield dut.ad.go.eq(0)
583 yield from wait_for(dut
.wr
.rel
[1])
584 yield dut
.wr
.go
.eq(0b10)
586 addr
= yield dut
.addr_o
588 yield dut
.wr
.go
.eq(0)
592 yield from wait_for(dut
.sto_rel_o
)
593 yield dut
.go_st_i
.eq(1)
595 yield dut
.go_st_i
.eq(0)
596 yield from wait_for(dut
.busy_o
, False)
597 #wait_for(dut.stwd_mem_o)
602 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
604 print ("LD", src1
, src2
, imm
, imm_ok
, update
)
605 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_LOAD
)
606 yield dut
.oper_i
.data_len
.eq(2) # half-word
607 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
608 yield dut
.src1_i
.eq(src1
)
609 yield dut
.src2_i
.eq(src2
)
610 yield dut
.oper_i
.zero_a
.eq(zero_a
)
611 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
612 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
613 yield dut
.issue_i
.eq(1)
615 yield dut
.issue_i
.eq(0)
618 # set up read-operand flags
620 if not imm_ok
: # no immediate means RB register needs to be read
622 if not zero_a
: # no zero-a means RA needs to be read
625 # wait for the operands (RA, RB, or both)
627 yield dut
.rd
.go
.eq(rd
)
628 yield from wait_for(dut
.rd
.rel
)
629 yield dut
.rd
.go
.eq(0)
631 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
632 #yield dut.ad.go.eq(1)
634 #yield dut.ad.go.eq(0)
637 yield from wait_for(dut
.wr
.rel
[1])
638 yield dut
.wr
.go
.eq(0b10)
640 addr
= yield dut
.addr_o
642 yield dut
.wr
.go
.eq(0)
646 yield from wait_for(dut
.wr
.rel
[0], test1st
=True)
647 yield dut
.wr
.go
.eq(1)
649 data
= yield dut
.data_o
651 yield dut
.wr
.go
.eq(0)
652 yield from wait_for(dut
.busy_o
)
654 # wait_for(dut.stwd_mem_o)
663 # two STs (different addresses)
664 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
665 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
667 # two LDs (deliberately LD from the 1st address then 2nd)
668 data
, addr
= yield from load(dut
, 4, 0, 2)
669 assert data
== 0x0003, "returned %x" % data
670 data
, addr
= yield from load(dut
, 2, 0, 2)
671 assert data
== 0x0009, "returned %x" % data
675 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
676 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
677 assert data
== 0x0003, "returned %x" % data
679 # update-immediate version
680 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
681 assert addr
== 0x000b, "returned %x" % addr
683 # update-indexed version
684 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
685 assert data
== 0x0003, "returned %x" % data
686 assert addr
== 0x000e, "returned %x" % addr
688 # immediate *and* zero version
689 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
690 assert data
== 0x0008, "returned %x" % data
693 class TestLDSTCompUnit(LDSTCompUnit
):
695 def __init__(self
, rwid
):
696 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
697 self
.l0
= l0
= TstL0CacheBuffer()
698 pi
= l0
.l0
.dports
[0].pi
699 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
701 def elaborate(self
, platform
):
702 m
= LDSTCompUnit
.elaborate(self
, platform
)
703 m
.submodules
.l0
= self
.l0
704 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
708 def test_scoreboard():
710 dut
= TestLDSTCompUnit(16)
711 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
712 with
open("test_ldst_comp.il", "w") as f
:
715 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
718 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
721 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
722 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
723 regspec
= LDSTPipeSpec
.regspec
724 self
.l0
= l0
= TstL0CacheBuffer()
725 pi
= l0
.l0
.dports
[0].pi
726 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
728 def elaborate(self
, platform
):
729 m
= LDSTCompUnit
.elaborate(self
, platform
)
730 m
.submodules
.l0
= self
.l0
731 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
735 def test_scoreboard_regspec():
737 dut
= TestLDSTCompUnitRegSpec()
738 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
739 with
open("test_ldst_comp.il", "w") as f
:
742 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
745 if __name__
== '__main__':
746 test_scoreboard_regspec()