3 This first version is intended for prototyping and test purposes:
4 it has "direct" access to Memory.
6 The intention is that this version remains an integral part of the
7 test infrastructure, and, just as with minerva's memory arrangement,
8 a dynamic runtime config *selects* alternative memory arrangements
9 rather than *replaces and discards* this code.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
18 from nmigen
.compat
.sim
import run_simulation
19 from nmigen
.cli
import verilog
, rtlil
20 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Array
, Cat
21 from nmutil
.iocontrol
import RecordObject
22 from nmigen
.utils
import log2_int
24 from nmutil
.latch
import SRLatch
, latchregister
25 from soc
.decoder
.power_decoder2
import Data
26 from soc
.decoder
.power_enums
import InternalOp
28 from soc
.experiment
.compldst
import CompLDSTOpSubset
29 from soc
.decoder
.power_decoder2
import Data
30 #from nmutil.picker import PriorityPicker
31 from nmigen
.lib
.coding
import PriorityEncoder
33 # for testing purposes
34 from soc
.experiment
.testmem
import TestMemory
37 class PortInterface(RecordObject
):
40 defines the interface - the API - that the LDSTCompUnit connects
41 to. note that this is NOT a "fire-and-forget" interface. the
42 LDSTCompUnit *must* be kept appraised that the request is in
43 progress, and only when it has a 100% successful completion rate
44 can the notification be given (busy dropped).
46 The interface FSM rules are as follows:
48 * if busy_o is asserted, a LD/ST is in progress. further
49 requests may not be made until busy_o is deasserted.
51 * only one of is_ld_i or is_st_i may be asserted. busy_o
52 will immediately be asserted and remain asserted.
54 * addr.ok is to be asserted when the LD/ST address is known.
55 addr.data is to be valid on the same cycle.
57 addr.ok and addr.data must REMAIN asserted until busy_o
58 is de-asserted. this ensures that there is no need
59 for the L0 Cache/Buffer to have an additional address latch
60 (because the LDSTCompUnit already has it)
62 * addr_ok_o (or addr_exc_o) must be waited for. these will
63 be asserted *only* for one cycle and one cycle only.
65 * addr_exc_o will be asserted if there is no chance that the
66 memory request may be fulfilled.
68 busy_o is deasserted on the same cycle as addr_exc_o is asserted.
70 * conversely: addr_ok_o must *ONLY* be asserted if there is a
71 HUNDRED PERCENT guarantee that the memory request will be
74 * for a LD, ld.ok will be asserted - for only one clock cycle -
75 at any point in the future that is acceptable to the underlying
76 Memory subsystem. the recipient MUST latch ld.data on that cycle.
78 busy_o is deasserted on the same cycle as ld.ok is asserted.
80 * for a ST, st.ok may be asserted only after addr_ok_o had been
81 asserted, alongside valid st.data at the same time. st.ok
82 must only be asserted for one cycle.
84 the underlying Memory is REQUIRED to pick up that data and
85 guarantee its delivery. no back-acknowledgement is required.
87 busy_o is deasserted on the same cycle as ld.ok is asserted.
90 def __init__(self
, name
=None, regwid
=64, addrwid
=48):
93 self
._addrwid
= addrwid
95 RecordObject
.__init
__(self
, name
=name
)
97 # distinguish op type (ld/st)
98 self
.is_ld_i
= Signal(reset_less
=True)
99 self
.is_st_i
= Signal(reset_less
=True)
100 self
.op
= CompLDSTOpSubset() # hm insn_type ld/st duplicates here
103 self
.busy_o
= Signal(reset_less
=True) # do not use if busy
104 self
.go_die_i
= Signal(reset_less
=True) # back to reset
105 self
.addr
= Data(addrwid
, "addr_i") # addr/addr-ok
106 self
.addr_ok_o
= Signal(reset_less
=True) # addr is valid (TLB, L1 etc.)
107 self
.addr_exc_o
= Signal(reset_less
=True) # TODO, "type" of exception
110 self
.ld
= Data(regwid
, "ld_data_o") # ok to be set by L0 Cache/Buf
111 self
.st
= Data(regwid
, "st_data_i") # ok to be set by CompUnit
114 class LDSTPort(Elaboratable
):
115 def __init__(self
, idx
, regwid
=64, addrwid
=48):
116 self
.pi
= PortInterface("ldst_port%d" % idx
, regwid
, addrwid
)
118 def elaborate(self
, platform
):
120 comb
, sync
= m
.d
.comb
, m
.d
.sync
123 m
.submodules
.busy_l
= busy_l
= SRLatch(False, name
="busy")
125 # this is a little weird: we let the L0Cache/Buffer set
126 # the outputs: this module just monitors "state".
128 # LD/ST requested activates "busy"
129 with m
.If(self
.pi
.is_ld_i | self
.pi
.is_st_i
):
130 comb
+= busy_l
.s
.eq(1)
132 # monitor for an exception or the completion of LD/ST.
133 with m
.If(self
.pi
.addr_exc_o | self
.pi
.ld
.ok | self
.pi
.st
.ok
):
134 comb
+= busy_l
.r
.eq(1)
136 # busy latch outputs to interface
137 comb
+= self
.pi
.busy_o
.eq(busy_l
.q
)
142 yield self
.pi
.is_ld_i
143 yield self
.pi
.is_st_i
144 yield from self
.pi
.op
.ports()
146 yield self
.pi
.go_die_i
147 yield from self
.pi
.addr
.ports()
148 yield self
.pi
.addr_ok_o
149 yield self
.pi
.addr_exc_o
151 yield from self
.pi
.ld
.ports()
152 yield from self
.pi
.st
.ports()
158 class L0CacheBuffer(Elaboratable
):
161 Note that the final version will have *two* interfaces per LDSTCompUnit,
162 to cover mis-aligned requests, as well as *two* 128-bit L1 Cache
163 interfaces: one for odd (addr[4] == 1) and one for even (addr[4] == 1).
165 This version is to be used for test purposes (and actively maintained
166 for such, rather than "replaced")
168 There are much better ways to implement this. However it's only
169 a "demo" / "test" class, and one important aspect: it responds
170 combinatorially, where a nmigen FSM's state-changes only activate
171 on clock-sync boundaries.
173 def __init__(self
, n_units
, mem
, regwid
=64, addrwid
=48):
174 self
.n_units
= n_units
177 for i
in range(n_units
):
178 ul
.append(LDSTPort(i
, regwid
, addrwid
))
179 self
.dports
= Array(ul
)
181 def elaborate(self
, platform
):
183 comb
, sync
= m
.d
.comb
, m
.d
.sync
185 # connect the ports as modules
186 for i
in range(self
.n_units
):
187 setattr(m
.submodules
, "port%d" % i
, self
.dports
[i
])
189 # state-machine latches
190 m
.submodules
.st_active
= st_active
= SRLatch(False, name
="st_active")
191 m
.submodules
.ld_active
= ld_active
= SRLatch(False, name
="ld_active")
192 m
.submodules
.reset_l
= reset_l
= SRLatch(True, name
="reset")
193 m
.submodules
.idx_l
= idx_l
= SRLatch(False, name
="idx_l")
194 m
.submodules
.adrok_l
= adrok_l
= SRLatch(True, name
="addr_acked")
196 # find one LD (or ST) and do it. only one per cycle.
197 # TODO: in the "live" (production) L0Cache/Buffer, merge multiple
198 # LD/STs using mask-expansion - see LenExpand class
200 m
.submodules
.ldpick
= ldpick
= PriorityEncoder(self
.n_units
)
201 m
.submodules
.stpick
= stpick
= PriorityEncoder(self
.n_units
)
203 lds
= Signal(self
.n_units
, reset_less
=True)
204 sts
= Signal(self
.n_units
, reset_less
=True)
207 for i
in range(self
.n_units
):
208 pi
= self
.dports
[i
].pi
209 ldi
.append(pi
.is_ld_i
& pi
.busy_o
) # accumulate ld-req signals
210 sti
.append(pi
.is_st_i
& pi
.busy_o
) # accumulate st-req signals
211 # put the requests into the priority-pickers
212 comb
+= ldpick
.i
.eq(Cat(*ldi
))
213 comb
+= stpick
.i
.eq(Cat(*sti
))
215 # hmm, have to select (record) the right port index
216 nbits
= log2_int(self
.n_units
, False)
217 ld_idx
= Signal(nbits
, reset_less
=False)
218 st_idx
= Signal(nbits
, reset_less
=False)
219 # use these because of the sync-and-comb pass-through capability
220 latchregister(m
, ldpick
.o
, ld_idx
, idx_l
.qn
, name
="ld_idx")
221 latchregister(m
, stpick
.o
, st_idx
, idx_l
.qn
, name
="st_idx")
223 # convenience variables to reference the "picked" port
224 ldport
= self
.dports
[ld_idx
].pi
225 stport
= self
.dports
[st_idx
].pi
226 # and the memory ports
227 rdport
= self
.mem
.rdport
228 wrport
= self
.mem
.wrport
230 # Priority-Pickers pick one and only one request, capture its index.
231 # from that point on this code *only* "listens" to that port.
233 with m
.If(~ldpick
.n
):
234 comb
+= ld_active
.s
.eq(1) # activate LD mode
235 comb
+= adrok_l
.r
.eq(1) # address not yet "ok'd"
236 comb
+= idx_l
.r
.eq(1) # pick (and capture) the port index
237 with m
.Elif(~stpick
.n
):
238 comb
+= st_active
.s
.eq(1) # activate ST mode
239 comb
+= adrok_l
.r
.eq(1) # address not yet "ok'd"
240 comb
+= idx_l
.r
.eq(1) # pick (and capture) the port index
242 # from this point onwards, with the port "picked", it stays picked
243 # until ld_active (or st_active) are de-asserted.
245 # if now in "LD" mode: wait for addr_ok, then send the address out
246 # to memory, acknowledge address, and send out LD data
247 with m
.If(ld_active
.q
):
248 with m
.If(ldport
.addr
.ok
):
249 comb
+= rdport
.addr
.eq(ldport
.addr
.data
) # addr ok, send thru
250 with m
.If(adrok_l
.qn
):
251 comb
+= ldport
.addr_ok_o
.eq(1) # acknowledge addr ok
252 comb
+= adrok_l
.s
.eq(1) # and pull "ack" latch
254 # if now in "ST" mode: likewise do the same but with "ST"
255 # to memory, acknowledge address, and send out LD data
256 with m
.If(st_active
.q
):
257 with m
.If(stport
.addr
.ok
):
258 comb
+= wrport
.addr
.eq(stport
.addr
.data
) # addr ok, send thru
259 with m
.If(adrok_l
.qn
):
260 comb
+= stport
.addr_ok_o
.eq(1) # acknowledge addr ok
261 comb
+= adrok_l
.s
.eq(1) # and pull "ack" latch
263 # NOTE: in both these, below, the port itself takes care
264 # of de-asserting its "busy_o" signal, based on either ld.ok going
265 # high (by us, here) or by st.ok going high (by the LDSTCompUnit).
267 # for LD mode, when addr has been "ok'd", assume that (because this
268 # is a "Memory" test-class) the memory read data is valid.
269 with m
.If(ld_active
.q
& adrok_l
.q
):
270 comb
+= ldport
.ld
.data
.eq(rdport
.data
) # put data out
271 comb
+= ldport
.ld
.ok
.eq(1) # indicate data valid
272 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
274 # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
275 with m
.If(st_active
.q
& adrok_l
.q
& stport
.st
.ok
):
276 comb
+= wrport
.data
.eq(stport
.st
.data
) # write st to mem
277 comb
+= wrport
.en
.eq(1) # enable write
278 comb
+= reset_l
.s
.eq(1) # reset mode after 1 cycle
280 with m
.If(reset_l
.q
):
281 comb
+= idx_l
.s
.eq(1) # deactivate port-index selector
282 comb
+= ld_active
.r
.eq(1) # leave the ST active for 1 cycle
283 comb
+= st_active
.r
.eq(1) # leave the ST active for 1 cycle
284 comb
+= reset_l
.r
.eq(1) # clear reset
289 for p
in self
.dports
:
293 class TstL0CacheBuffer(Elaboratable
):
294 def __init__(self
, n_units
=3, regwid
=16, addrwid
=4):
295 self
.mem
= TestMemory(regwid
, addrwid
)
296 self
.l0
= L0CacheBuffer(n_units
, self
.mem
, regwid
, addrwid
)
298 def elaborate(self
, platform
):
300 m
.submodules
.mem
= self
.mem
301 m
.submodules
.l0
= self
.l0
306 yield from self
.l0
.ports()
307 yield self
.mem
.rdport
.addr
308 yield self
.mem
.rdport
.data
309 yield self
.mem
.wrport
.addr
310 yield self
.mem
.wrport
.data
313 def wait_busy(port
, no
=False):
315 busy
= yield port
.pi
.busy_o
316 print ("busy", no
, busy
)
324 addr_ok
= yield port
.pi
.addr_ok_o
325 print ("addrok", addr_ok
)
332 ldok
= yield port
.pi
.ld
.ok
338 def l0_cache_st(dut
, addr
, data
):
344 # set up a ST on the port. address first:
345 yield port1
.pi
.is_st_i
.eq(1) # indicate LD
346 yield from wait_busy(port1
) # wait until busy
348 yield port1
.pi
.addr
.data
.eq(addr
) # set address
349 yield port1
.pi
.addr
.ok
.eq(1) # set ok
350 yield from wait_addr(port1
) # wait until addr ok
352 yield # no idea why this needs to be done.
354 # assert "ST" for one cycle (required by the API)
355 yield port1
.pi
.st
.data
.eq(data
)
356 yield port1
.pi
.st
.ok
.eq(1)
360 yield from wait_busy(port1
, no
=True) # wait until not busy
361 yield port1
.pi
.st
.ok
.eq(0)
362 yield port1
.pi
.is_st_i
.eq(0) #end
363 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
366 def l0_cache_ld(dut
, addr
, expected
):
372 # set up a LD on the port. address first:
373 yield port1
.pi
.is_ld_i
.eq(1) # indicate LD
374 yield from wait_busy(port1
) # wait until busy
376 yield port1
.pi
.addr
.data
.eq(addr
) # set address
377 yield port1
.pi
.addr
.ok
.eq(1) # set ok
378 yield from wait_addr(port1
) # wait until addr ok
380 yield from wait_ldok(port1
) # wait until ld ok
381 data
= yield port1
.pi
.ld
.data
384 yield from wait_busy(port1
, no
=True) # wait until not busy
385 yield port1
.pi
.is_ld_i
.eq(0) #end
386 yield port1
.pi
.addr
.ok
.eq(0) # set !ok
388 assert data
== expected
, "data %x != %x" % (data
, expected
)
390 def l0_cache_ldst(dut
):
395 yield from l0_cache_st(dut
, addr
, data
)
400 yield from l0_cache_ld(dut
, addr
, data
)
407 dut
= TstL0CacheBuffer()
408 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
409 with
open("test_basic_l0_cache.il", "w") as f
:
412 run_simulation(dut
, l0_cache_ldst(dut
),
413 vcd_name
='test_l0_cache_basic.vcd')
416 if __name__
== '__main__':