src/soc/experiment/mem_types.py

   1 """mem_types
   2
   3 based on Anton Blanchard microwatt common.vhdl
   4
   5 """
   6 from nmutil.iocontrol import RecordObject
   7 from nmigen import Signal
   8
   9
  10 class LoadStore1ToMmuType(RecordObject):
  11     def __init__(self):
  12         super().__init__()
  13         self.valid = Signal()
  14         self.tlbie = Signal()
  15         self.slbia = Signal()
  16         self.mtspr = Signal()
  17         self.iside = Signal()
  18         self.load  = Signal()
  19         self.priv  = Signal()
  20         self.sprn  = Signal(10)
  21         self.addr  = Signal(64)
  22         self.rs    = Signal(64)
  23
  24
  25 class MmuToLoadStore1Type(RecordObject):
  26     def __init__(self):
  27         super().__init__()
  28         self.done       = Signal()
  29         self.err        = Signal()
  30         self.invalid    = Signal()
  31         self.badtree    = Signal()
  32         self.segerr     = Signal()
  33         self.perm_error = Signal()
  34         self.rc_error   = Signal()
  35         self.sprval     = Signal(64)
  36
  37
  38 class MmuToDcacheType(RecordObject):
  39     def __init__(self):
  40         super().__init__()
  41         self.valid = Signal()
  42         self.tlbie = Signal()
  43         self.doall = Signal()
  44         self.tlbld = Signal()
  45         self.addr  = Signal(64)
  46         self.pte   = Signal(64)
  47
  48
  49 class DcacheToMmuType(RecordObject):
  50     def __init__(self):
  51         super().__init__()
  52         self.stall = Signal()
  53         self.done  = Signal()
  54         self.err   = Signal()
  55         self.data  = Signal(64)
  56
  57
  58
  59 class MmuToIcacheType(RecordObject):
  60     def __init__(self):
  61         super().__init__()
  62         self.tlbld = Signal()
  63         self.tlbie = Signal()
  64         self.doall = Signal()
  65         self.addr  = Signal(64)
  66         self.pte   = Signal(64)
  67
  68
  69 class LoadStore1ToDcacheType(RecordObject):
  70     def __init__(self):
  71         super().__init__()
  72         self.valid     = Signal()
  73         self.load      = Signal() # this is a load
  74         self.dcbz      = Signal()
  75         self.nc        = Signal()
  76         self.nc        = Signal()
  77         self.reserve   = Signal()
  78         self.virt_mode = Signal()
  79         self.priv_mode = Signal()
  80         self.addr      = Signal()
  81         self.data      = Signal()
  82         self.byte_sel  = Signal()
  83
  84
  85 class DcacheToLoadStore1Type(RecordObject):
  86     def __init__(self):
  87         super().__init__()
  88         self.valid         = Signal()
  89         self.data          = Signal()
  90         self.store_done    = Signal()
  91         self.error         = Signal()
  92         self.cache_paradox = Signal()