radix: reading first page table entry
[soc.git] / src / soc / experiment / mem_types.py
1 """mem_types
2
3 based on Anton Blanchard microwatt common.vhdl
4
5 """
6 from nmutil.iocontrol import RecordObject
7 from nmigen import Signal
8
9 # https://bugs.libre-soc.org/show_bug.cgi?id=465
10 class LDSTException(RecordObject):
11 _exc_types = ['happened', 'alignment', 'instr_fault', 'invalid', 'badtree',
12 'perm_error', 'rc_error', 'segment_fault',]
13 def __init__(self, name=None):
14 RecordObject.__init__(self, name=name)
15 for f in self._exc_types:
16 setattr(self, f, Signal())
17
18
19 class DCacheToLoadStore1Type(RecordObject):
20 def __init__(self, name=None):
21 super().__init__(name=name)
22 self.valid = Signal()
23 self.data = Signal(64)
24 self.store_done = Signal()
25 self.error = Signal()
26 self.cache_paradox = Signal()
27
28
29 class DCacheToMMUType(RecordObject):
30 def __init__(self, name=None):
31 super().__init__(name=name)
32 self.stall = Signal()
33 self.done = Signal()
34 self.err = Signal()
35 self.data = Signal(64)
36
37
38 class Fetch1ToICacheType(RecordObject):
39 def __init__(self, name=None):
40 super().__init__(name=name)
41 self.req = Signal()
42 self.virt_mode = Signal()
43 self.priv_mode = Signal()
44 self.stop_mark = Signal()
45 self.sequential = Signal()
46 self.nia = Signal(64)
47
48
49 class ICacheToDecode1Type(RecordObject):
50 def __init__(self, name=None):
51 super().__init__(name=name)
52 self.valid = Signal()
53 self.stop_mark = Signal()
54 self.fetch_failed = Signal()
55 self.nia = Signal(64)
56 self.insn = Signal(32)
57
58
59 class LoadStore1ToDCacheType(RecordObject):
60 def __init__(self, name=None):
61 super().__init__(name=name)
62 self.valid = Signal()
63 self.load = Signal() # this is a load
64 self.dcbz = Signal()
65 self.nc = Signal()
66 self.reserve = Signal()
67 self.virt_mode = Signal()
68 self.priv_mode = Signal()
69 self.addr = Signal(64)
70 self.data = Signal(64)
71 self.byte_sel = Signal(8)
72
73
74 class LoadStore1ToMMUType(RecordObject):
75 def __init__(self, name=None):
76 super().__init__(name=name)
77 self.valid = Signal()
78 self.tlbie = Signal()
79 self.slbia = Signal()
80 self.mtspr = Signal()
81 self.iside = Signal()
82 self.load = Signal()
83 self.priv = Signal()
84 self.sprn = Signal(10)
85 self.addr = Signal(64)
86 self.rs = Signal(64)
87
88
89 class MMUToLoadStore1Type(RecordObject):
90 def __init__(self, name=None):
91 super().__init__(name=name)
92 self.done = Signal()
93 self.err = Signal()
94 self.invalid = Signal()
95 self.badtree = Signal()
96 self.segerr = Signal()
97 self.perm_error = Signal()
98 self.rc_error = Signal()
99 self.sprval = Signal(64)
100
101
102 class MMUToDCacheType(RecordObject):
103 def __init__(self, name=None):
104 super().__init__(name=name)
105 self.valid = Signal()
106 self.tlbie = Signal()
107 self.doall = Signal()
108 self.tlbld = Signal()
109 self.addr = Signal(64)
110 self.pte = Signal(64)
111
112
113 class MMUToICacheType(RecordObject):
114 def __init__(self, name=None):
115 super().__init__(name=name)
116 self.tlbld = Signal()
117 self.tlbie = Signal()
118 self.doall = Signal()
119 self.addr = Signal(64)
120 self.pte = Signal(64)
121