src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15 * https://bugs.libre-soc.org/show_bug.cgi?id=465 - exception handling
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation, Settle
  20 from nmigen.cli import rtlil
  21 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  22 from nmutil.iocontrol import RecordObject
  23 from nmigen.utils import log2_int
  24
  25 from nmutil.latch import SRLatch, latchregister
  26 from nmutil.util import rising_edge
  27 from openpower.decoder.power_decoder2 import Data
  28 from soc.scoreboard.addr_match import LenExpand
  29 from soc.experiment.mem_types import LDSTException
  30
  31 # for testing purposes
  32 from soc.experiment.testmem import TestMemory
  33 #from soc.scoreboard.addr_split import LDSTSplitter
  34
  35 import unittest
  36
  37
  38 class PortInterface(RecordObject):
  39     """PortInterface
  40
  41     defines the interface - the API - that the LDSTCompUnit connects
  42     to.  note that this is NOT a "fire-and-forget" interface.  the
  43     LDSTCompUnit *must* be kept appraised that the request is in
  44     progress, and only when it has a 100% successful completion
  45     can the notification be given (busy dropped).
  46
  47     The interface FSM rules are as follows:
  48
  49     * if busy_o is asserted, a LD/ST is in progress.  further
  50       requests may not be made until busy_o is deasserted.
  51
  52     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  53       will immediately be asserted and remain asserted.
  54
  55     * addr.ok is to be asserted when the LD/ST address is known.
  56       addr.data is to be valid on the same cycle.
  57
  58       addr.ok and addr.data must REMAIN asserted until busy_o
  59       is de-asserted.  this ensures that there is no need
  60       for the L0 Cache/Buffer to have an additional address latch
  61       (because the LDSTCompUnit already has it)
  62
  63     * addr_ok_o (or exception.happened) must be waited for.  these will
  64       be asserted *only* for one cycle and one cycle only.
  65
  66     * exception.happened will be asserted if there is no chance that the
  67       memory request may be fulfilled.
  68
  69       busy_o is deasserted on the same cycle as exception.happened is asserted.
  70
  71     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  72       HUNDRED PERCENT guarantee that the memory request will be
  73       fulfilled.
  74
  75     * for a LD, ld.ok will be asserted - for only one clock cycle -
  76       at any point in the future that is acceptable to the underlying
  77       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  78
  79       busy_o is deasserted on the same cycle as ld.ok is asserted.
  80
  81     * for a ST, st.ok may be asserted only after addr_ok_o had been
  82       asserted, alongside valid st.data at the same time.  st.ok
  83       must only be asserted for one cycle.
  84
  85       the underlying Memory is REQUIRED to pick up that data and
  86       guarantee its delivery.  no back-acknowledgement is required.
  87
  88       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  89     """
  90
  91     def __init__(self, name=None, regwid=64, addrwid=48):
  92
  93         self._regwid = regwid
  94         self._addrwid = addrwid
  95
  96         RecordObject.__init__(self, name=name)
  97
  98         # distinguish op type (ld/st)
  99         self.is_ld_i = Signal(reset_less=True)
 100         self.is_st_i = Signal(reset_less=True)
 101
 102         # LD/ST data length (TODO: other things may be needed)
 103         self.data_len = Signal(4, reset_less=True)
 104
 105         # common signals
 106         self.busy_o = Signal(reset_less=True)     # do not use if busy
 107         self.go_die_i = Signal(reset_less=True)   # back to reset
 108         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 109         # addr is valid (TLB, L1 etc.)
 110         self.addr_ok_o = Signal(reset_less=True)
 111         self.exc_o = LDSTException("exc")
 112
 113         # LD/ST
 114         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 115         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 116
 117         # additional "modes"
 118         self.is_dcbz        = Signal()  # data cache block zero request
 119         self.is_nc         = Signal()  # no cacheing
 120         self.msr_pr        = Signal()  # 1==virtual, 0==privileged
 121
 122         # mmu
 123         self.mmu_done          = Signal() # keep for now
 124
 125         # dcache
 126         self.ldst_error        = Signal()
 127         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 128         self.cache_paradox     = Signal()
 129
 130     def connect_port(self, inport):
 131         print("connect_port", self, inport)
 132         return [self.is_ld_i.eq(inport.is_ld_i),
 133                 self.is_st_i.eq(inport.is_st_i),
 134                 self.is_nc.eq(inport.is_nc),
 135                 self.is_dcbz.eq(inport.is_dcbz),
 136                 self.data_len.eq(inport.data_len),
 137                 self.go_die_i.eq(inport.go_die_i),
 138                 self.addr.data.eq(inport.addr.data),
 139                 self.addr.ok.eq(inport.addr.ok),
 140                 self.st.eq(inport.st),
 141                 self.msr_pr.eq(inport.msr_pr),
 142                 inport.ld.eq(self.ld),
 143                 inport.busy_o.eq(self.busy_o),
 144                 inport.addr_ok_o.eq(self.addr_ok_o),
 145                 inport.exc_o.eq(self.exc_o),
 146                 inport.mmu_done.eq(self.mmu_done),
 147                 inport.ldst_error.eq(self.ldst_error),
 148                 inport.cache_paradox.eq(self.cache_paradox)
 149                 ]
 150
 151
 152 class PortInterfaceBase(Elaboratable):
 153     """PortInterfaceBase
 154
 155     Base class for PortInterface-compliant Memory read/writers
 156     """
 157
 158     def __init__(self, regwid=64, addrwid=4):
 159         self.regwid = regwid
 160         self.addrwid = addrwid
 161         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 162
 163     @property
 164     def addrbits(self):
 165         return log2_int(self.regwid//8)
 166
 167     def splitaddr(self, addr):
 168         """split the address into top and bottom bits of the memory granularity
 169         """
 170         return addr[:self.addrbits], addr[self.addrbits:]
 171
 172     def connect_port(self, inport):
 173         return self.pi.connect_port(inport)
 174
 175     def set_wr_addr(self, m, addr, mask, misalign, msr_pr): pass
 176     def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
 177     def set_wr_data(self, m, data, wen): pass
 178     def get_rd_data(self, m): pass
 179
 180     def elaborate(self, platform):
 181         m = Module()
 182         comb, sync = m.d.comb, m.d.sync
 183
 184         # state-machine latches
 185         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 186         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 187         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 188         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 189         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 190         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 191         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 192
 193         self.busy_l = busy_l
 194
 195         sync += st_done.s.eq(0)
 196         comb += st_done.r.eq(0)
 197         comb += st_active.r.eq(0)
 198         comb += ld_active.r.eq(0)
 199         comb += cyc_l.s.eq(0)
 200         comb += cyc_l.r.eq(0)
 201         comb += busy_l.s.eq(0)
 202         comb += busy_l.r.eq(0)
 203         sync += adrok_l.s.eq(0)
 204         comb += adrok_l.r.eq(0)
 205
 206         # expand ld/st binary length/addr[:3] into unary bitmap
 207         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 208
 209         lds = Signal(reset_less=True)
 210         sts = Signal(reset_less=True)
 211         pi = self.pi
 212         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 213         comb += sts.eq(pi.is_st_i)  # st-req signals
 214         pr = pi.msr_pr # MSR problem state: PR=1 ==> virt, PR==0 ==> priv
 215
 216         # detect busy "edge"
 217         busy_delay = Signal()
 218         busy_edge = Signal()
 219         sync += busy_delay.eq(pi.busy_o)
 220         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 221
 222         # misalignment detection: bits at end of lenexpand are set.
 223         # when using the L0CacheBuffer "data expander" which splits requests
 224         # into *two* PortInterfaces, this acts as a "safety check".
 225         misalign = Signal()
 226         comb += misalign.eq(lenexp.lexp_o[8:].bool())
 227
 228
 229         # activate mode: only on "edge"
 230         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 231         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 232
 233         # LD/ST requested activates "busy" (only if not already busy)
 234         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 235             comb += busy_l.s.eq(~busy_delay)
 236
 237         # if now in "LD" mode: wait for addr_ok, then send the address out
 238         # to memory, acknowledge address, and send out LD data
 239         with m.If(ld_active.q):
 240             # set up LenExpander with the LD len and lower bits of addr
 241             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 242             comb += lenexp.len_i.eq(pi.data_len)
 243             comb += lenexp.addr_i.eq(lsbaddr)
 244             with m.If(pi.addr.ok & adrok_l.qn):
 245                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 246                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 247                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 248
 249         # if now in "ST" mode: likewise do the same but with "ST"
 250         # to memory, acknowledge address, and send out LD data
 251         with m.If(st_active.q):
 252             # set up LenExpander with the ST len and lower bits of addr
 253             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 254             comb += lenexp.len_i.eq(pi.data_len)
 255             comb += lenexp.addr_i.eq(lsbaddr)
 256             with m.If(pi.addr.ok):
 257                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o, misalign, pr)
 258                 with m.If(adrok_l.qn):
 259                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 260                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 261
 262         # for LD mode, when addr has been "ok'd", assume that (because this
 263         # is a "Memory" test-class) the memory read data is valid.
 264         comb += reset_l.s.eq(0)
 265         comb += reset_l.r.eq(0)
 266         lddata = Signal(self.regwid, reset_less=True)
 267         data, ldok = self.get_rd_data(m)
 268         comb += lddata.eq((data & lenexp.rexp_o) >>
 269                           (lenexp.addr_i*8))
 270         with m.If(ld_active.q & adrok_l.q):
 271             # shift data down before pushing out.  requires masking
 272             # from the *byte*-expanded version of LenExpand output
 273             comb += pi.ld.data.eq(lddata)  # put data out
 274             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 275             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 276
 277         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 278         with m.If(st_active.q & pi.st.ok):
 279             # shift data up before storing.  lenexp *bit* version of mask is
 280             # passed straight through as byte-level "write-enable" lines.
 281             stdata = Signal(self.regwid, reset_less=True)
 282             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 283             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 284             # and also handle the ready/stall/busy protocol
 285             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 286             sync += st_done.s.eq(1)     # store done trigger
 287         with m.If(st_done.q):
 288             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 289
 290         # ugly hack, due to simultaneous addr req-go acknowledge
 291         reset_delay = Signal(reset_less=True)
 292         sync += reset_delay.eq(reset_l.q)
 293         with m.If(reset_delay):
 294             comb += adrok_l.r.eq(1)     # address reset
 295
 296         # after waiting one cycle (reset_l is "sync" mode), reset the port
 297         with m.If(reset_l.q):
 298             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 299             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 300             comb += reset_l.r.eq(1)     # clear reset
 301             comb += adrok_l.r.eq(1)     # address reset
 302             comb += st_done.r.eq(1)     # store done reset
 303
 304         # monitor for an exception, clear busy immediately
 305         with m.If(self.pi.exc_o.happened):
 306             comb += busy_l.r.eq(1)
 307
 308         # however ST needs one cycle before busy is reset
 309         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 310         with m.If(reset_l.s):
 311             comb += cyc_l.s.eq(1)
 312
 313         with m.If(cyc_l.q):
 314             comb += cyc_l.r.eq(1)
 315             comb += busy_l.r.eq(1)
 316
 317         # busy latch outputs to interface
 318         comb += pi.busy_o.eq(busy_l.q)
 319
 320         return m
 321
 322     def ports(self):
 323         yield from self.pi.ports()
 324
 325
 326 class TestMemoryPortInterface(PortInterfaceBase):
 327     """TestMemoryPortInterface
 328
 329     This is a test class for simple verification of the LDSTCompUnit
 330     and for the simple core, to be able to run unit tests rapidly and
 331     with less other code in the way.
 332
 333     Versions of this which are *compatible* (conform with PortInterface)
 334     will include augmented-Wishbone Bus versions, including ones that
 335     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 336     possible version that complies with PortInterface".
 337     """
 338
 339     def __init__(self, regwid=64, addrwid=4):
 340         super().__init__(regwid, addrwid)
 341         # hard-code memory addressing width to 6 bits
 342         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 343
 344     def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
 345         lsbaddr, msbaddr = self.splitaddr(addr)
 346         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 347
 348     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
 349         lsbaddr, msbaddr = self.splitaddr(addr)
 350         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 351
 352     def set_wr_data(self, m, data, wen):
 353         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 354         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 355         return Const(1, 1)
 356
 357     def get_rd_data(self, m):
 358         return self.mem.rdport.data, Const(1, 1)
 359
 360     def elaborate(self, platform):
 361         m = super().elaborate(platform)
 362
 363         # add TestMemory as submodule
 364         m.submodules.mem = self.mem
 365
 366         return m
 367
 368     def ports(self):
 369         yield from super().ports()
 370         # TODO: memory ports