src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23
  24 from nmutil.latch import SRLatch, latchregister
  25 from nmutil.util import rising_edge
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.scoreboard.addr_match import LenExpand
  28
  29 # for testing purposes
  30 from soc.experiment.testmem import TestMemory
  31 #from soc.scoreboard.addr_split import LDSTSplitter
  32
  33
  34 import unittest
  35
  36
  37 class PortInterface(RecordObject):
  38     """PortInterface
  39
  40     defines the interface - the API - that the LDSTCompUnit connects
  41     to.  note that this is NOT a "fire-and-forget" interface.  the
  42     LDSTCompUnit *must* be kept appraised that the request is in
  43     progress, and only when it has a 100% successful completion
  44     can the notification be given (busy dropped).
  45
  46     The interface FSM rules are as follows:
  47
  48     * if busy_o is asserted, a LD/ST is in progress.  further
  49       requests may not be made until busy_o is deasserted.
  50
  51     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  52       will immediately be asserted and remain asserted.
  53
  54     * addr.ok is to be asserted when the LD/ST address is known.
  55       addr.data is to be valid on the same cycle.
  56
  57       addr.ok and addr.data must REMAIN asserted until busy_o
  58       is de-asserted.  this ensures that there is no need
  59       for the L0 Cache/Buffer to have an additional address latch
  60       (because the LDSTCompUnit already has it)
  61
  62     * addr_ok_o (or addr_exc_o) must be waited for.  these will
  63       be asserted *only* for one cycle and one cycle only.
  64
  65     * addr_exc_o will be asserted if there is no chance that the
  66       memory request may be fulfilled.
  67
  68       busy_o is deasserted on the same cycle as addr_exc_o is asserted.
  69
  70     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  71       HUNDRED PERCENT guarantee that the memory request will be
  72       fulfilled.
  73
  74     * for a LD, ld.ok will be asserted - for only one clock cycle -
  75       at any point in the future that is acceptable to the underlying
  76       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  77
  78       busy_o is deasserted on the same cycle as ld.ok is asserted.
  79
  80     * for a ST, st.ok may be asserted only after addr_ok_o had been
  81       asserted, alongside valid st.data at the same time.  st.ok
  82       must only be asserted for one cycle.
  83
  84       the underlying Memory is REQUIRED to pick up that data and
  85       guarantee its delivery.  no back-acknowledgement is required.
  86
  87       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  88     """
  89
  90     def __init__(self, name=None, regwid=64, addrwid=48):
  91
  92         self._regwid = regwid
  93         self._addrwid = addrwid
  94
  95         RecordObject.__init__(self, name=name)
  96
  97         # distinguish op type (ld/st)
  98         self.is_ld_i = Signal(reset_less=True)
  99         self.is_st_i = Signal(reset_less=True)
 100
 101         # LD/ST data length (TODO: other things may be needed)
 102         self.data_len = Signal(4, reset_less=True)
 103
 104         # common signals
 105         self.busy_o = Signal(reset_less=True)     # do not use if busy
 106         self.go_die_i = Signal(reset_less=True)   # back to reset
 107         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 108         # addr is valid (TLB, L1 etc.)
 109         self.addr_ok_o = Signal(reset_less=True)
 110         self.addr_exc_o = Signal(reset_less=True)  # TODO, "type" of exception
 111
 112         # LD/ST
 113         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 114         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 115
 116         # additional "modes"
 117         self.dcbz          = Signal()  # data cache block zero request
 118         self.nc            = Signal()  # no cacheing
 119         self.virt_mode     = Signal()  # virtual mode
 120         self.priv_mode     = Signal()  # privileged mode
 121
 122     def connect_port(self, inport):
 123         print("connect_port", self, inport)
 124         return [self.is_ld_i.eq(inport.is_ld_i),
 125                 self.is_st_i.eq(inport.is_st_i),
 126                 self.data_len.eq(inport.data_len),
 127                 self.go_die_i.eq(inport.go_die_i),
 128                 self.addr.data.eq(inport.addr.data),
 129                 self.addr.ok.eq(inport.addr.ok),
 130                 self.st.eq(inport.st),
 131                 inport.ld.eq(self.ld),
 132                 inport.busy_o.eq(self.busy_o),
 133                 inport.addr_ok_o.eq(self.addr_ok_o),
 134                 inport.addr_exc_o.eq(self.addr_exc_o),
 135                 ]
 136
 137
 138 class PortInterfaceBase(Elaboratable):
 139     """PortInterfaceBase
 140
 141     Base class for PortInterface-compliant Memory read/writers
 142     """
 143
 144     def __init__(self, regwid=64, addrwid=4):
 145         self.regwid = regwid
 146         self.addrwid = addrwid
 147         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 148
 149     @property
 150     def addrbits(self):
 151         return log2_int(self.regwid//8)
 152
 153     def splitaddr(self, addr):
 154         """split the address into top and bottom bits of the memory granularity
 155         """
 156         return addr[:self.addrbits], addr[self.addrbits:]
 157
 158     def connect_port(self, inport):
 159         return self.pi.connect_port(inport)
 160
 161     def set_wr_addr(self, m, addr, mask): pass
 162     def set_rd_addr(self, m, addr, mask): pass
 163     def set_wr_data(self, m, data, wen): pass
 164     def get_rd_data(self, m): pass
 165
 166     def elaborate(self, platform):
 167         m = Module()
 168         comb, sync = m.d.comb, m.d.sync
 169
 170         # state-machine latches
 171         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 172         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 173         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 174         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 175         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 176         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 177         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 178
 179         self.busy_l = busy_l
 180
 181         sync += st_done.s.eq(0)
 182         comb += st_done.r.eq(0)
 183         comb += st_active.r.eq(0)
 184         comb += ld_active.r.eq(0)
 185         comb += cyc_l.s.eq(0)
 186         comb += cyc_l.r.eq(0)
 187         comb += busy_l.s.eq(0)
 188         comb += busy_l.r.eq(0)
 189         sync += adrok_l.s.eq(0)
 190         comb += adrok_l.r.eq(0)
 191
 192         # expand ld/st binary length/addr[:3] into unary bitmap
 193         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 194
 195         lds = Signal(reset_less=True)
 196         sts = Signal(reset_less=True)
 197         pi = self.pi
 198         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 199         comb += sts.eq(pi.is_st_i)  # st-req signals
 200
 201         # detect busy "edge"
 202         busy_delay = Signal()
 203         busy_edge = Signal()
 204         sync += busy_delay.eq(pi.busy_o)
 205         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 206
 207         # activate mode: only on "edge"
 208         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 209         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 210
 211         # LD/ST requested activates "busy" (only if not already busy)
 212         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 213             comb += busy_l.s.eq(~busy_delay)
 214
 215         # if now in "LD" mode: wait for addr_ok, then send the address out
 216         # to memory, acknowledge address, and send out LD data
 217         with m.If(ld_active.q):
 218             # set up LenExpander with the LD len and lower bits of addr
 219             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 220             comb += lenexp.len_i.eq(pi.data_len)
 221             comb += lenexp.addr_i.eq(lsbaddr)
 222             with m.If(pi.addr.ok & adrok_l.qn):
 223                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
 224                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 225                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 226
 227         # if now in "ST" mode: likewise do the same but with "ST"
 228         # to memory, acknowledge address, and send out LD data
 229         with m.If(st_active.q):
 230             # set up LenExpander with the ST len and lower bits of addr
 231             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 232             comb += lenexp.len_i.eq(pi.data_len)
 233             comb += lenexp.addr_i.eq(lsbaddr)
 234             with m.If(pi.addr.ok):
 235                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o)
 236                 with m.If(adrok_l.qn):
 237                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 238                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 239
 240         # for LD mode, when addr has been "ok'd", assume that (because this
 241         # is a "Memory" test-class) the memory read data is valid.
 242         comb += reset_l.s.eq(0)
 243         comb += reset_l.r.eq(0)
 244         lddata = Signal(self.regwid, reset_less=True)
 245         data, ldok = self.get_rd_data(m)
 246         comb += lddata.eq((data & lenexp.rexp_o) >>
 247                           (lenexp.addr_i*8))
 248         with m.If(ld_active.q & adrok_l.q):
 249             # shift data down before pushing out.  requires masking
 250             # from the *byte*-expanded version of LenExpand output
 251             comb += pi.ld.data.eq(lddata)  # put data out
 252             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 253             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 254
 255         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 256         with m.If(st_active.q & pi.st.ok):
 257             # shift data up before storing.  lenexp *bit* version of mask is
 258             # passed straight through as byte-level "write-enable" lines.
 259             stdata = Signal(self.regwid, reset_less=True)
 260             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 261             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 262             # and also handle the ready/stall/busy protocol
 263             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 264             sync += st_done.s.eq(1)     # store done trigger
 265         with m.If(st_done.q):
 266             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 267
 268         # ugly hack, due to simultaneous addr req-go acknowledge
 269         reset_delay = Signal(reset_less=True)
 270         sync += reset_delay.eq(reset_l.q)
 271         with m.If(reset_delay):
 272             comb += adrok_l.r.eq(1)     # address reset
 273
 274         # after waiting one cycle (reset_l is "sync" mode), reset the port
 275         with m.If(reset_l.q):
 276             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 277             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 278             comb += reset_l.r.eq(1)     # clear reset
 279             comb += adrok_l.r.eq(1)     # address reset
 280             comb += st_done.r.eq(1)     # store done reset
 281
 282         # monitor for an exception or the completion of LD.
 283         with m.If(self.pi.addr_exc_o):
 284             comb += busy_l.r.eq(1)
 285
 286         # however ST needs one cycle before busy is reset
 287         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 288         with m.If(reset_l.s):
 289             comb += cyc_l.s.eq(1)
 290
 291         with m.If(cyc_l.q):
 292             comb += cyc_l.r.eq(1)
 293             comb += busy_l.r.eq(1)
 294
 295         # busy latch outputs to interface
 296         comb += pi.busy_o.eq(busy_l.q)
 297
 298         return m
 299
 300     def ports(self):
 301         yield from self.pi.ports()
 302
 303
 304 class TestMemoryPortInterface(PortInterfaceBase):
 305     """TestMemoryPortInterface
 306
 307     This is a test class for simple verification of the LDSTCompUnit
 308     and for the simple core, to be able to run unit tests rapidly and
 309     with less other code in the way.
 310
 311     Versions of this which are *compatible* (conform with PortInterface)
 312     will include augmented-Wishbone Bus versions, including ones that
 313     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 314     possible version that complies with PortInterface".
 315     """
 316
 317     def __init__(self, regwid=64, addrwid=4):
 318         super().__init__(regwid, addrwid)
 319         # hard-code memory addressing width to 6 bits
 320         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 321
 322     def set_wr_addr(self, m, addr, mask):
 323         lsbaddr, msbaddr = self.splitaddr(addr)
 324         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 325
 326     def set_rd_addr(self, m, addr, mask):
 327         lsbaddr, msbaddr = self.splitaddr(addr)
 328         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 329
 330     def set_wr_data(self, m, data, wen):
 331         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 332         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 333         return Const(1, 1)
 334
 335     def get_rd_data(self, m):
 336         return self.mem.rdport.data, Const(1, 1)
 337
 338     def elaborate(self, platform):
 339         m = super().elaborate(platform)
 340
 341         # add TestMemory as submodule
 342         m.submodules.mem = self.mem
 343
 344         return m
 345
 346     def ports(self):
 347         yield from super().ports()
 348         # TODO: memory ports