src/soc/experiment/pimem.py

   1 """L0 Cache/Buffer
   2
   3 This first version is intended for prototyping and test purposes:
   4 it has "direct" access to Memory.
   5
   6 The intention is that this version remains an integral part of the
   7 test infrastructure, and, just as with minerva's memory arrangement,
   8 a dynamic runtime config *selects* alternative memory arrangements
   9 rather than *replaces and discards* this code.
  10
  11 Links:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=216
  14 * https://libre-soc.org/3d_gpu/architecture/memory_and_cache/
  15
  16 """
  17
  18 from nmigen.compat.sim import run_simulation, Settle
  19 from nmigen.cli import rtlil
  20 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
  21 from nmutil.iocontrol import RecordObject
  22 from nmigen.utils import log2_int
  23
  24 from nmutil.latch import SRLatch, latchregister
  25 from nmutil.util import rising_edge
  26 from soc.decoder.power_decoder2 import Data
  27 from soc.scoreboard.addr_match import LenExpand
  28 from soc.experiment.mem_types import LDSTException
  29
  30 # for testing purposes
  31 from soc.experiment.testmem import TestMemory
  32 #from soc.scoreboard.addr_split import LDSTSplitter
  33
  34 import unittest
  35
  36
  37 class PortInterface(RecordObject):
  38     """PortInterface
  39
  40     defines the interface - the API - that the LDSTCompUnit connects
  41     to.  note that this is NOT a "fire-and-forget" interface.  the
  42     LDSTCompUnit *must* be kept appraised that the request is in
  43     progress, and only when it has a 100% successful completion
  44     can the notification be given (busy dropped).
  45
  46     The interface FSM rules are as follows:
  47
  48     * if busy_o is asserted, a LD/ST is in progress.  further
  49       requests may not be made until busy_o is deasserted.
  50
  51     * only one of is_ld_i or is_st_i may be asserted.  busy_o
  52       will immediately be asserted and remain asserted.
  53
  54     * addr.ok is to be asserted when the LD/ST address is known.
  55       addr.data is to be valid on the same cycle.
  56
  57       addr.ok and addr.data must REMAIN asserted until busy_o
  58       is de-asserted.  this ensures that there is no need
  59       for the L0 Cache/Buffer to have an additional address latch
  60       (because the LDSTCompUnit already has it)
  61
  62     * addr_ok_o (or exception.happened) must be waited for.  these will
  63       be asserted *only* for one cycle and one cycle only.
  64
  65     * exception.happened will be asserted if there is no chance that the
  66       memory request may be fulfilled.
  67
  68       busy_o is deasserted on the same cycle as exception.happened is asserted.
  69
  70     * conversely: addr_ok_o must *ONLY* be asserted if there is a
  71       HUNDRED PERCENT guarantee that the memory request will be
  72       fulfilled.
  73
  74     * for a LD, ld.ok will be asserted - for only one clock cycle -
  75       at any point in the future that is acceptable to the underlying
  76       Memory subsystem.  the recipient MUST latch ld.data on that cycle.
  77
  78       busy_o is deasserted on the same cycle as ld.ok is asserted.
  79
  80     * for a ST, st.ok may be asserted only after addr_ok_o had been
  81       asserted, alongside valid st.data at the same time.  st.ok
  82       must only be asserted for one cycle.
  83
  84       the underlying Memory is REQUIRED to pick up that data and
  85       guarantee its delivery.  no back-acknowledgement is required.
  86
  87       busy_o is deasserted on the cycle AFTER st.ok is asserted.
  88     """
  89
  90     def __init__(self, name=None, regwid=64, addrwid=48):
  91
  92         self._regwid = regwid
  93         self._addrwid = addrwid
  94
  95         RecordObject.__init__(self, name=name)
  96
  97         # distinguish op type (ld/st)
  98         self.is_ld_i = Signal(reset_less=True)
  99         self.is_st_i = Signal(reset_less=True)
 100
 101         # LD/ST data length (TODO: other things may be needed)
 102         self.data_len = Signal(4, reset_less=True)
 103
 104         # common signals
 105         self.busy_o = Signal(reset_less=True)     # do not use if busy
 106         self.go_die_i = Signal(reset_less=True)   # back to reset
 107         self.addr = Data(addrwid, "addr_i")            # addr/addr-ok
 108         # addr is valid (TLB, L1 etc.)
 109         self.addr_ok_o = Signal(reset_less=True)
 110         self.exception_o = LDSTException("exc")
 111
 112         # LD/ST
 113         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
 114         self.st = Data(regwid, "st_data_i")  # ok to be set by CompUnit
 115
 116         # additional "modes"
 117         self.dcbz          = Signal()  # data cache block zero request
 118         self.nc            = Signal()  # no cacheing
 119         self.virt_mode     = Signal()  # virtual mode
 120         self.priv_mode     = Signal()  # privileged mode
 121
 122         # mmu
 123         self.mmu_done          = Signal()
 124         self.mmu_err           = Signal()
 125         self.mmu_invalid       = Signal()
 126         # radix tree is invalid
 127         self.mmu_badtree       = Signal()
 128         # segment_check fails
 129         self.mmu_segerr        = Signal()
 130         # permission error takes precedence over RC error
 131         self.mmu_perm_error    = Signal()
 132         self.mmu_rc_error      = Signal()
 133         # r.prtbl or r.pid
 134         self.mmu_sprval        = Signal(64)
 135
 136         # dcache
 137         self.ldst_error        = Signal()
 138         ## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
 139         self.cache_paradox     = Signal()
 140
 141     def connect_port(self, inport):
 142         print("connect_port", self, inport)
 143         return [self.is_ld_i.eq(inport.is_ld_i),
 144                 self.is_st_i.eq(inport.is_st_i),
 145                 self.data_len.eq(inport.data_len),
 146                 self.go_die_i.eq(inport.go_die_i),
 147                 self.addr.data.eq(inport.addr.data),
 148                 self.addr.ok.eq(inport.addr.ok),
 149                 self.st.eq(inport.st),
 150                 inport.ld.eq(self.ld),
 151                 inport.busy_o.eq(self.busy_o),
 152                 inport.addr_ok_o.eq(self.addr_ok_o),
 153                 inport.exception_o.eq(self.exception_o),
 154                 ]
 155
 156
 157 class PortInterfaceBase(Elaboratable):
 158     """PortInterfaceBase
 159
 160     Base class for PortInterface-compliant Memory read/writers
 161     """
 162
 163     def __init__(self, regwid=64, addrwid=4):
 164         self.regwid = regwid
 165         self.addrwid = addrwid
 166         self.pi = PortInterface("ldst_port0", regwid, addrwid)
 167
 168     @property
 169     def addrbits(self):
 170         return log2_int(self.regwid//8)
 171
 172     def splitaddr(self, addr):
 173         """split the address into top and bottom bits of the memory granularity
 174         """
 175         return addr[:self.addrbits], addr[self.addrbits:]
 176
 177     def connect_port(self, inport):
 178         return self.pi.connect_port(inport)
 179
 180     def set_wr_addr(self, m, addr, mask): pass
 181     def set_rd_addr(self, m, addr, mask): pass
 182     def set_wr_data(self, m, data, wen): pass
 183     def get_rd_data(self, m): pass
 184
 185     def elaborate(self, platform):
 186         m = Module()
 187         comb, sync = m.d.comb, m.d.sync
 188
 189         # state-machine latches
 190         m.submodules.st_active = st_active = SRLatch(False, name="st_active")
 191         m.submodules.st_done = st_done = SRLatch(False, name="st_done")
 192         m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
 193         m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
 194         m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
 195         m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
 196         m.submodules.cyc_l = cyc_l = SRLatch(True, name="cyc")
 197
 198         self.busy_l = busy_l
 199
 200         sync += st_done.s.eq(0)
 201         comb += st_done.r.eq(0)
 202         comb += st_active.r.eq(0)
 203         comb += ld_active.r.eq(0)
 204         comb += cyc_l.s.eq(0)
 205         comb += cyc_l.r.eq(0)
 206         comb += busy_l.s.eq(0)
 207         comb += busy_l.r.eq(0)
 208         sync += adrok_l.s.eq(0)
 209         comb += adrok_l.r.eq(0)
 210
 211         # expand ld/st binary length/addr[:3] into unary bitmap
 212         m.submodules.lenexp = lenexp = LenExpand(4, 8)
 213
 214         lds = Signal(reset_less=True)
 215         sts = Signal(reset_less=True)
 216         pi = self.pi
 217         comb += lds.eq(pi.is_ld_i)  # ld-req signals
 218         comb += sts.eq(pi.is_st_i)  # st-req signals
 219
 220         # detect busy "edge"
 221         busy_delay = Signal()
 222         busy_edge = Signal()
 223         sync += busy_delay.eq(pi.busy_o)
 224         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 225
 226         # activate mode: only on "edge"
 227         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
 228         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 229
 230         # LD/ST requested activates "busy" (only if not already busy)
 231         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
 232             comb += busy_l.s.eq(~busy_delay)
 233
 234         # if now in "LD" mode: wait for addr_ok, then send the address out
 235         # to memory, acknowledge address, and send out LD data
 236         with m.If(ld_active.q):
 237             # set up LenExpander with the LD len and lower bits of addr
 238             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 239             comb += lenexp.len_i.eq(pi.data_len)
 240             comb += lenexp.addr_i.eq(lsbaddr)
 241             with m.If(pi.addr.ok & adrok_l.qn):
 242                 self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
 243                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 244                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 245
 246         # if now in "ST" mode: likewise do the same but with "ST"
 247         # to memory, acknowledge address, and send out LD data
 248         with m.If(st_active.q):
 249             # set up LenExpander with the ST len and lower bits of addr
 250             lsbaddr, msbaddr = self.splitaddr(pi.addr.data)
 251             comb += lenexp.len_i.eq(pi.data_len)
 252             comb += lenexp.addr_i.eq(lsbaddr)
 253             with m.If(pi.addr.ok):
 254                 self.set_wr_addr(m, pi.addr.data, lenexp.lexp_o)
 255                 with m.If(adrok_l.qn):
 256                     comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
 257                     sync += adrok_l.s.eq(1)       # and pull "ack" latch
 258
 259         # for LD mode, when addr has been "ok'd", assume that (because this
 260         # is a "Memory" test-class) the memory read data is valid.
 261         comb += reset_l.s.eq(0)
 262         comb += reset_l.r.eq(0)
 263         lddata = Signal(self.regwid, reset_less=True)
 264         data, ldok = self.get_rd_data(m)
 265         comb += lddata.eq((data & lenexp.rexp_o) >>
 266                           (lenexp.addr_i*8))
 267         with m.If(ld_active.q & adrok_l.q):
 268             # shift data down before pushing out.  requires masking
 269             # from the *byte*-expanded version of LenExpand output
 270             comb += pi.ld.data.eq(lddata)  # put data out
 271             comb += pi.ld.ok.eq(ldok)      # indicate data valid
 272             comb += reset_l.s.eq(ldok)     # reset mode after 1 cycle
 273
 274         # for ST mode, when addr has been "ok'd", wait for incoming "ST ok"
 275         with m.If(st_active.q & pi.st.ok):
 276             # shift data up before storing.  lenexp *bit* version of mask is
 277             # passed straight through as byte-level "write-enable" lines.
 278             stdata = Signal(self.regwid, reset_less=True)
 279             comb += stdata.eq(pi.st.data << (lenexp.addr_i*8))
 280             # TODO: replace with link to LoadStoreUnitInterface.x_store_data
 281             # and also handle the ready/stall/busy protocol
 282             stok = self.set_wr_data(m, stdata, lenexp.lexp_o)
 283             sync += st_done.s.eq(1)     # store done trigger
 284         with m.If(st_done.q):
 285             comb += reset_l.s.eq(stok)   # reset mode after 1 cycle
 286
 287         # ugly hack, due to simultaneous addr req-go acknowledge
 288         reset_delay = Signal(reset_less=True)
 289         sync += reset_delay.eq(reset_l.q)
 290         with m.If(reset_delay):
 291             comb += adrok_l.r.eq(1)     # address reset
 292
 293         # after waiting one cycle (reset_l is "sync" mode), reset the port
 294         with m.If(reset_l.q):
 295             comb += ld_active.r.eq(1)   # leave the ST active for 1 cycle
 296             comb += st_active.r.eq(1)   # leave the ST active for 1 cycle
 297             comb += reset_l.r.eq(1)     # clear reset
 298             comb += adrok_l.r.eq(1)     # address reset
 299             comb += st_done.r.eq(1)     # store done reset
 300
 301         # monitor for an exception or the completion of LD.
 302         with m.If(self.pi.exception_o.happened):
 303             comb += busy_l.r.eq(1)
 304
 305         # however ST needs one cycle before busy is reset
 306         #with m.If(self.pi.st.ok | self.pi.ld.ok):
 307         with m.If(reset_l.s):
 308             comb += cyc_l.s.eq(1)
 309
 310         with m.If(cyc_l.q):
 311             comb += cyc_l.r.eq(1)
 312             comb += busy_l.r.eq(1)
 313
 314         # busy latch outputs to interface
 315         comb += pi.busy_o.eq(busy_l.q)
 316
 317         return m
 318
 319     def ports(self):
 320         yield from self.pi.ports()
 321
 322
 323 class TestMemoryPortInterface(PortInterfaceBase):
 324     """TestMemoryPortInterface
 325
 326     This is a test class for simple verification of the LDSTCompUnit
 327     and for the simple core, to be able to run unit tests rapidly and
 328     with less other code in the way.
 329
 330     Versions of this which are *compatible* (conform with PortInterface)
 331     will include augmented-Wishbone Bus versions, including ones that
 332     connect to L1, L2, MMU etc. etc. however this is the "base lowest
 333     possible version that complies with PortInterface".
 334     """
 335
 336     def __init__(self, regwid=64, addrwid=4):
 337         super().__init__(regwid, addrwid)
 338         # hard-code memory addressing width to 6 bits
 339         self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False)
 340
 341     def set_wr_addr(self, m, addr, mask):
 342         lsbaddr, msbaddr = self.splitaddr(addr)
 343         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 344
 345     def set_rd_addr(self, m, addr, mask):
 346         lsbaddr, msbaddr = self.splitaddr(addr)
 347         m.d.comb += self.mem.rdport.addr.eq(msbaddr)
 348
 349     def set_wr_data(self, m, data, wen):
 350         m.d.comb += self.mem.wrport.data.eq(data)  # write st to mem
 351         m.d.comb += self.mem.wrport.en.eq(wen)  # enable writes
 352         return Const(1, 1)
 353
 354     def get_rd_data(self, m):
 355         return self.mem.rdport.data, Const(1, 1)
 356
 357     def elaborate(self, platform):
 358         m = super().elaborate(platform)
 359
 360         # add TestMemory as submodule
 361         m.submodules.mem = self.mem
 362
 363         return m
 364
 365     def ports(self):
 366         yield from super().ports()
 367         # TODO: memory ports