src/soc/experiment/sim.py

   1 from soc.decoder.power_enums import InternalOp
   2
   3 from random import randint, seed
   4 from copy import deepcopy
   5 from math import log
   6
   7
   8 class MemSim:
   9     def __init__(self, regwid, addrw):
  10         self.regwid = regwid
  11         self.ddepth = 1 # regwid//8
  12         depth = (1<<addrw) // self.ddepth
  13         self.mem = list(range(0, depth))
  14
  15     def ld(self, addr):
  16         return self.mem[addr>>self.ddepth]
  17
  18     def st(self, addr, data):
  19         self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
  20
  21
  22
  23 IADD = 0
  24 ISUB = 1
  25 IMUL = 2
  26 ISHF = 3
  27 IBGT = 4
  28 IBLT = 5
  29 IBEQ = 6
  30 IBNE = 7
  31
  32
  33 class RegSim:
  34     def __init__(self, rwidth, nregs):
  35         self.rwidth = rwidth
  36         self.regs = [0] * nregs
  37
  38     def op(self, op, op_imm, imm, src1, src2, dest):
  39         print ("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
  40         maxbits = (1 << self.rwidth) - 1
  41         src1 = self.regs[src1] & maxbits
  42         if op_imm:
  43             src2 = imm
  44         else:
  45             src2 = self.regs[src2] & maxbits
  46         if op == InternalOp.OP_ADD:
  47             val = src1 + src2
  48         elif op == InternalOp.OP_MUL_L64:
  49             val = src1 * src2
  50             print ("mul src1, src2", src1, src2, val)
  51         elif op == ISUB:
  52             val = src1 - src2
  53         elif op == ISHF:
  54             val = src1 >> (src2 & maxbits)
  55         elif op == IBGT:
  56             val = int(src1 > src2)
  57         elif op == IBLT:
  58             val = int(src1 < src2)
  59         elif op == IBEQ:
  60             val = int(src1 == src2)
  61         elif op == IBNE:
  62             val = int(src1 != src2)
  63         else:
  64             return 0 # LD/ST TODO
  65         val &= maxbits
  66         self.setval(dest, val)
  67         return val
  68
  69     def setval(self, dest, val):
  70         print ("sim setval", dest, hex(val))
  71         self.regs[dest] = val
  72
  73     def dump(self, dut):
  74         for i, val in enumerate(self.regs):
  75             reg = yield dut.intregs.regs[i].reg
  76             okstr = "OK" if reg == val else "!ok"
  77             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
  78
  79     def check(self, dut):
  80         for i, val in enumerate(self.regs):
  81             reg = yield dut.intregs.regs[i].reg
  82             if reg != val:
  83                 print("reg %d expected %x received %x\n" % (i, val, reg))
  84                 yield from self.dump(dut)
  85                 assert False
  86