src/soc/experiment/sim.py

   1 from soc.decoder.power_enums import MicrOp
   2
   3 from random import randint, seed
   4 from copy import deepcopy
   5 from math import log
   6
   7
   8 class MemSim:
   9     def __init__(self, regwid, addrw):
  10         self.regwid = regwid
  11         self.ddepth = 1  # regwid//8
  12         depth = (1 << addrw) // self.ddepth
  13         self.mem = list(range(0, depth))
  14
  15     def ld(self, addr):
  16         return self.mem[addr >> self.ddepth]
  17
  18     def st(self, addr, data):
  19         self.mem[addr >> self.ddepth] = data & ((1 << self.regwid)-1)
  20
  21
  22 IADD = 0
  23 ISUB = 1
  24 IMUL = 2
  25 ISHF = 3
  26 IBGT = 4
  27 IBLT = 5
  28 IBEQ = 6
  29 IBNE = 7
  30
  31
  32 class RegSim:
  33     def __init__(self, rwidth, nregs):
  34         self.rwidth = rwidth
  35         self.regs = [0] * nregs
  36
  37     def op(self, op, op_imm, imm, src1, src2, dest):
  38         print("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
  39         maxbits = (1 << self.rwidth) - 1
  40         src1 = self.regs[src1] & maxbits
  41         if op_imm:
  42             src2 = imm
  43         else:
  44             src2 = self.regs[src2] & maxbits
  45         if op == MicrOp.OP_ADD:
  46             val = src1 + src2
  47         elif op == MicrOp.OP_MUL_L64:
  48             val = src1 * src2
  49             print("mul src1, src2", src1, src2, val)
  50         elif op == ISUB:
  51             val = src1 - src2
  52         elif op == ISHF:
  53             val = src1 >> (src2 & maxbits)
  54         elif op == IBGT:
  55             val = int(src1 > src2)
  56         elif op == IBLT:
  57             val = int(src1 < src2)
  58         elif op == IBEQ:
  59             val = int(src1 == src2)
  60         elif op == IBNE:
  61             val = int(src1 != src2)
  62         else:
  63             return 0  # LD/ST TODO
  64         val &= maxbits
  65         self.setval(dest, val)
  66         return val
  67
  68     def setval(self, dest, val):
  69         print("sim setval", dest, hex(val))
  70         self.regs[dest] = val
  71
  72     def dump(self, dut):
  73         for i, val in enumerate(self.regs):
  74             reg = yield dut.intregs.regs[i].reg
  75             okstr = "OK" if reg == val else "!ok"
  76             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
  77
  78     def check(self, dut):
  79         for i, val in enumerate(self.regs):
  80             reg = yield dut.intregs.regs[i].reg
  81             if reg != val:
  82                 print("reg %d expected %x received %x\n" % (i, val, reg))
  83                 yield from self.dump(dut)
  84                 assert False