src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.fu.cr.cr_input_record import CompCROpSubset
  16 from soc.experiment.alu_hier import ALU, DummyALU
  17 from soc.experiment.compalu_multi import MultiCompUnit
  18 from soc.decoder.power_enums import MicrOp
  19 from nmutil.gtkw import write_gtkw
  20 from nmigen import Module, Signal
  21 from nmigen.cli import rtlil
  22
  23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  25 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  26                                         Passive)
  27
  28
  29 def wrap(process):
  30     def wrapper():
  31         yield from process
  32     return wrapper
  33
  34
  35 class OperandProducer:
  36     """
  37     Produces an operand when requested by the Computation Unit
  38     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  39
  40     Attaches itself to the `dut` operand indexed by `op_index`.
  41
  42     Has a programmable delay between the assertion of `rel_o` and the
  43     `go_i` pulse.
  44
  45     Data is presented only during the cycle in which `go_i` is active.
  46
  47     It adds itself as a passive process to the simulation (`sim` parameter).
  48     Since it is passive, it will not hang the simulation, and does not need a
  49     flag to terminate itself.
  50     """
  51     def __init__(self, sim, dut, op_index):
  52         self.count = Signal(8, name=f"src{op_index + 1}_count")
  53         """ transaction counter"""
  54         # data and handshake signals from the DUT
  55         self.port = dut.src_i[op_index]
  56         self.go_i = dut.rd.go_i[op_index]
  57         self.rel_o = dut.rd.rel_o[op_index]
  58         # transaction parameters, passed via signals
  59         self.delay = Signal(8)
  60         self.data = Signal.like(self.port)
  61         # add ourselves to the simulation process list
  62         sim.add_sync_process(self._process)
  63
  64     def _process(self):
  65         yield Passive()
  66         while True:
  67             # Settle() is needed to give a quick response to
  68             # the zero delay case
  69             yield Settle()
  70             # wait for rel_o to become active
  71             while not (yield self.rel_o):
  72                 yield
  73                 yield Settle()
  74             # read the transaction parameters
  75             delay = (yield self.delay)
  76             data = (yield self.data)
  77             # wait for `delay` cycles
  78             for _ in range(delay):
  79                 yield
  80             # activate go_i and present data, for one cycle
  81             yield self.go_i.eq(1)
  82             yield self.port.eq(data)
  83             yield self.count.eq(self.count + 1)
  84             yield
  85             yield self.go_i.eq(0)
  86             yield self.port.eq(0)
  87
  88     def send(self, data, delay):
  89         """
  90         Schedules the module to send some `data`, counting `delay` cycles after
  91         `rel_i` becomes active.
  92
  93         To be called from the main test-bench process,
  94         it returns in the same cycle.
  95
  96         Communication with the worker process is done by means of
  97         combinatorial simulation-only signals.
  98
  99         """
 100         yield self.data.eq(data)
 101         yield self.delay.eq(delay)
 102
 103
 104 class ResultConsumer:
 105     """
 106     Consumes a result when requested by the Computation Unit
 107     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 108
 109     Attaches itself to the `dut` result indexed by `op_index`.
 110
 111     Has a programmable delay between the assertion of `rel_o` and the
 112     `go_i` pulse.
 113
 114     Data is retrieved only during the cycle in which `go_i` is active.
 115
 116     It adds itself as a passive process to the simulation (`sim` parameter).
 117     Since it is passive, it will not hang the simulation, and does not need a
 118     flag to terminate itself.
 119     """
 120     def __init__(self, sim, dut, op_index):
 121         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 122         """ transaction counter"""
 123         # data and handshake signals from the DUT
 124         self.port = dut.dest[op_index]
 125         self.go_i = dut.wr.go_i[op_index]
 126         self.rel_o = dut.wr.rel_o[op_index]
 127         # transaction parameters, passed via signals
 128         self.delay = Signal(8)
 129         self.expected = Signal.like(self.port)
 130         # add ourselves to the simulation process list
 131         sim.add_sync_process(self._process)
 132
 133     def _process(self):
 134         yield Passive()
 135         while True:
 136             # Settle() is needed to give a quick response to
 137             # the zero delay case
 138             yield Settle()
 139             # wait for rel_o to become active
 140             while not (yield self.rel_o):
 141                 yield
 142                 yield Settle()
 143             # read the transaction parameters
 144             delay = (yield self.delay)
 145             expected = (yield self.expected)
 146             # wait for `delay` cycles
 147             for _ in range(delay):
 148                 yield
 149             # activate go_i for one cycle
 150             yield self.go_i.eq(1)
 151             yield self.count.eq(self.count + 1)
 152             yield
 153             # check received data against the expected value
 154             result = (yield self.port)
 155             assert result == expected,\
 156                 f"expected {expected}, received {result}"
 157             yield self.go_i.eq(0)
 158             yield self.port.eq(0)
 159
 160     def receive(self, expected, delay):
 161         """
 162         Schedules the module to receive some result,
 163         counting `delay` cycles after `rel_i` becomes active.
 164         As 'go_i' goes active, check the result with `expected`.
 165
 166         To be called from the main test-bench process,
 167         it returns in the same cycle.
 168
 169         Communication with the worker process is done by means of
 170         combinatorial simulation-only signals.
 171         """
 172         yield self.expected.eq(expected)
 173         yield self.delay.eq(delay)
 174
 175
 176 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 177     yield dut.issue_i.eq(0)
 178     yield
 179     yield dut.src_i[0].eq(a)
 180     yield dut.src_i[1].eq(b)
 181     yield dut.oper_i.insn_type.eq(op)
 182     yield dut.oper_i.invert_in.eq(inv_a)
 183     yield dut.oper_i.imm_data.data.eq(imm)
 184     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 185     yield dut.oper_i.zero_a.eq(zero_a)
 186     yield dut.issue_i.eq(1)
 187     yield
 188     yield dut.issue_i.eq(0)
 189     yield
 190     if not imm_ok or not zero_a:
 191         yield dut.rd.go_i.eq(0b11)
 192         while True:
 193             yield
 194             rd_rel_o = yield dut.rd.rel_o
 195             print("rd_rel", rd_rel_o)
 196             if rd_rel_o:
 197                 break
 198         yield dut.rd.go_i.eq(0)
 199     else:
 200         print("no go rd")
 201
 202     if len(dut.src_i) == 3:
 203         yield dut.rd.go_i.eq(0b100)
 204         while True:
 205             yield
 206             rd_rel_o = yield dut.rd.rel_o
 207             print("rd_rel", rd_rel_o)
 208             if rd_rel_o:
 209                 break
 210         yield dut.rd.go_i.eq(0)
 211     else:
 212         print("no 3rd rd")
 213
 214     req_rel_o = yield dut.wr.rel_o
 215     result = yield dut.data_o
 216     print("req_rel", req_rel_o, result)
 217     while True:
 218         req_rel_o = yield dut.wr.rel_o
 219         result = yield dut.data_o
 220         print("req_rel", req_rel_o, result)
 221         if req_rel_o:
 222             break
 223         yield
 224     yield dut.wr.go_i[0].eq(1)
 225     yield Settle()
 226     result = yield dut.data_o
 227     yield
 228     print("result", result)
 229     yield dut.wr.go_i[0].eq(0)
 230     yield
 231     return result
 232
 233
 234 def scoreboard_sim_fsm(dut, producers, consumers):
 235
 236     # stores the operation count
 237     op_count = 0
 238
 239     def op_sim_fsm(a, b, direction, expected, delays):
 240         print("op_sim_fsm", a, b, direction, expected)
 241         yield dut.issue_i.eq(0)
 242         yield
 243         # forward data and delays to the producers and consumers
 244         yield from producers[0].send(a, delays[0])
 245         yield from producers[1].send(b, delays[1])
 246         yield from consumers[0].receive(expected, delays[2])
 247         # submit operation, and assert issue_i for one cycle
 248         yield dut.oper_i.sdir.eq(direction)
 249         yield dut.issue_i.eq(1)
 250         yield
 251         yield dut.issue_i.eq(0)
 252         # wait for busy to be negated
 253         yield Settle()
 254         while (yield dut.busy_o):
 255             yield
 256             yield Settle()
 257         # update the operation count
 258         nonlocal op_count
 259         op_count = (op_count + 1) & 255
 260         # check that producers and consumers have the same count
 261         # this assures that no data was left unused or was lost
 262         assert (yield producers[0].count) == op_count
 263         assert (yield producers[1].count) == op_count
 264         assert (yield consumers[0].count) == op_count
 265
 266     # 13 >> 2 = 3
 267     # operand 1 arrives immediately
 268     # operand 2 arrives after operand 1
 269     # write data is accepted immediately
 270     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 271     # 3 << 4 = 48
 272     # operand 2 arrives immediately
 273     # operand 1 arrives after operand 2
 274     # write data is accepted after some delay
 275     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 276     # 21 << 0 = 21
 277     # operands 1 and 2 arrive at the same time
 278     # write data is accepted after some delay
 279     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 280
 281
 282 def scoreboard_sim_dummy(op):
 283     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 284                         src_delays=[0, 2, 1], dest_delays=[0])
 285     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 286                         src_delays=[2, 1, 0], dest_delays=[2])
 287
 288
 289 class OpSim:
 290     """ALU Operation issuer
 291
 292     Issues operations to the DUT"""
 293     def __init__(self, dut, sim):
 294         self.op_count = 0
 295         self.zero_a_count = 0
 296         self.imm_ok_count = 0
 297         self.dut = dut
 298         # create one operand producer for each input port
 299         self.producers = list()
 300         for i in range(len(dut.src_i)):
 301             self.producers.append(OperandProducer(sim, dut, i))
 302         # create one result consumer for each output port
 303         self.consumers = list()
 304         for i in range(len(dut.dest)):
 305             self.consumers.append(ResultConsumer(sim, dut, i))
 306     def issue(self, src_i, op, expected, src_delays, dest_delays,
 307               inv_a=0, imm=0, imm_ok=0, zero_a=0):
 308         """Executes the issue operation"""
 309         dut = self.dut
 310         producers = self.producers
 311         consumers = self.consumers
 312         yield dut.issue_i.eq(0)
 313         yield
 314         # forward data and delays to the producers and consumers
 315         # first, send special cases (with zero_a and/or imm_ok)
 316         if not zero_a:
 317             yield from producers[0].send(src_i[0], src_delays[0])
 318         if not imm_ok:
 319             yield from producers[1].send(src_i[1], src_delays[1])
 320         # then, send the rest (if any)
 321         for i in range(2, len(producers)):
 322             yield from producers[i].send(src_i[i], src_delays[i])
 323         for i in range(len(consumers)):
 324             yield from consumers[i].receive(expected[i], dest_delays[i])
 325         # submit operation, and assert issue_i for one cycle
 326         yield dut.oper_i.insn_type.eq(op)
 327         if hasattr(dut.oper_i, "invert_in"):
 328             yield dut.oper_i.invert_in.eq(inv_a)
 329         if hasattr(dut.oper_i, "imm_data"):
 330             yield dut.oper_i.imm_data.data.eq(imm)
 331             yield dut.oper_i.imm_data.ok.eq(imm_ok)
 332         if hasattr(dut.oper_i, "zero_a"):
 333             yield dut.oper_i.zero_a.eq(zero_a)
 334         yield dut.issue_i.eq(1)
 335         yield
 336         yield dut.issue_i.eq(0)
 337         # wait for busy to be negated
 338         yield Settle()
 339         while (yield dut.busy_o):
 340             yield
 341             yield Settle()
 342         # update the operation count
 343         self.op_count = (self.op_count + 1) & 255
 344         # On zero_a and imm_ok executions, the producer counters will fall
 345         # behind. But, by summing the following counts, the invariant is
 346         # preserved.
 347         if zero_a:
 348             self.zero_a_count = self.zero_a_count + 1
 349         if imm_ok:
 350             self.imm_ok_count = self.imm_ok_count + 1
 351         # check that producers and consumers have the same count
 352         # this assures that no data was left unused or was lost
 353         # first, check special cases (zero_a and imm_ok)
 354         assert (yield producers[0].count) + self.zero_a_count == self.op_count
 355         assert (yield producers[1].count) + self.imm_ok_count == self.op_count
 356         # then, check the rest (if any)
 357         for i in range(2, len(producers)):
 358             assert (yield producers[i].count) == self.op_count
 359         for i in range(len(consumers)):
 360             assert (yield consumers[i].count) == self.op_count
 361
 362
 363 def scoreboard_sim(op):
 364     # zero (no) input operands test
 365     # 0 + 8 = 8
 366     yield from op.issue([5, 2], MicrOp.OP_ADD, [8],
 367                         zero_a=1, imm=8, imm_ok=1,
 368                         src_delays=[0, 2], dest_delays=[0])
 369     # 5 + 8 = 13
 370     yield from op.issue([5, 2], MicrOp.OP_ADD, [13],
 371                         inv_a=0, imm=8, imm_ok=1,
 372                         src_delays=[2, 0], dest_delays=[2])
 373     # 5 + 2 = 7
 374     yield from op.issue([5, 2], MicrOp.OP_ADD, [7],
 375                         src_delays=[1, 1], dest_delays=[1])
 376     # (-6) + 2 = (-4)
 377     yield from op.issue([5, 2], MicrOp.OP_ADD, [65532],
 378                         inv_a=1,
 379                         src_delays=[1, 2], dest_delays=[0])
 380     # 0 + 2 = 2
 381     yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
 382                         zero_a=1,
 383                         src_delays=[2, 0], dest_delays=[1])
 384
 385     # test combinatorial zero-delay operation
 386     # In the test ALU, any operation other than ADD, MUL or SHR
 387     # is zero-delay, and do a subtraction.
 388     # 5 - 2 = 3
 389     yield from op.issue([5, 2], MicrOp.OP_NOP, [3],
 390                         src_delays=[0, 1], dest_delays=[2])
 391
 392
 393 def test_compunit_fsm():
 394     style = {
 395         'in': {'color': 'orange'},
 396         'out': {'color': 'yellow'},
 397     }
 398     traces = [
 399         'clk',
 400         ('operation port', {'color': 'red'}, [
 401             'cu_issue_i', 'cu_busy_o',
 402             {'comment': 'operation'},
 403             'oper_i_None__sdir']),
 404         ('operand 1 port', 'in', [
 405             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 406             ('cu_rd__go_i[1:0]', {'bit': 1}),
 407             'src1_i[7:0]']),
 408         ('operand 2 port', 'in', [
 409             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 410             ('cu_rd__go_i[1:0]', {'bit': 0}),
 411             'src2_i[7:0]']),
 412         ('result port', 'out', [
 413             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 414         ('alu', {'submodule': 'alu'}, [
 415             ('prev port', 'in', [
 416                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 417                 ({'submodule': 'p'},
 418                     ['p_valid_i', 'p_ready_o'])]),
 419             ('next port', 'out', [
 420                 'n_data_o[7:0]',
 421                 ({'submodule': 'n'},
 422                     ['n_valid_o', 'n_ready_i'])])]),
 423         ('debug', {'module': 'top'},
 424             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 425
 426     write_gtkw(
 427         "test_compunit_fsm1.gtkw",
 428         "test_compunit_fsm1.vcd",
 429         traces, style,
 430         module='top.cu'
 431     )
 432     m = Module()
 433     alu = Shifter(8)
 434     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 435     m.submodules.cu = dut
 436
 437     vl = rtlil.convert(dut, ports=dut.ports())
 438     with open("test_compunit_fsm1.il", "w") as f:
 439         f.write(vl)
 440
 441     sim = Simulator(m)
 442     sim.add_clock(1e-6)
 443
 444     # create one operand producer for each input port
 445     prod_a = OperandProducer(sim, dut, 0)
 446     prod_b = OperandProducer(sim, dut, 1)
 447     # create an result consumer for the output port
 448     cons = ResultConsumer(sim, dut, 0)
 449     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 450                                                  [prod_a, prod_b],
 451                                                  [cons])))
 452     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 453                                traces=[prod_a.count,
 454                                        prod_b.count,
 455                                        cons.count])
 456     with sim_writer:
 457         sim.run()
 458
 459
 460 def test_compunit():
 461
 462     m = Module()
 463     alu = ALU(16)
 464     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 465     m.submodules.cu = dut
 466
 467     vl = rtlil.convert(dut, ports=dut.ports())
 468     with open("test_compunit1.il", "w") as f:
 469         f.write(vl)
 470
 471     sim = Simulator(m)
 472     sim.add_clock(1e-6)
 473
 474     # create an operation issuer
 475     op = OpSim(dut, sim)
 476     sim.add_sync_process(wrap(scoreboard_sim(op)))
 477     sim_writer = sim.write_vcd('test_compunit1.vcd')
 478     with sim_writer:
 479         sim.run()
 480
 481
 482 class CompUnitParallelTest:
 483     def __init__(self, dut):
 484         self.dut = dut
 485
 486         # Operation cycle should not take longer than this:
 487         self.MAX_BUSY_WAIT = 50
 488
 489         # Minimum duration in which issue_i will be kept inactive,
 490         # during which busy_o must remain low.
 491         self.MIN_BUSY_LOW = 5
 492
 493         # Number of cycles to stall until the assertion of go.
 494         # One value, for each port. Can be zero, for no delay.
 495         self.RD_GO_DELAY = [0, 3]
 496
 497         # store common data for the input operation of the processes
 498         # input operation:
 499         self.op = 0
 500         self.inv_a = self.zero_a = 0
 501         self.imm = self.imm_ok = 0
 502         self.imm_control = (0, 0)
 503         self.rdmaskn = (0, 0)
 504         # input data:
 505         self.operands = (0, 0)
 506
 507         # Indicates completion of the sub-processes
 508         self.rd_complete = [False, False]
 509
 510     def driver(self):
 511         print("Begin parallel test.")
 512         yield from self.operation(5, 2, MicrOp.OP_ADD)
 513
 514     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 515                   rdmaskn=(0, 0)):
 516         # store data for the operation
 517         self.operands = (a, b)
 518         self.op = op
 519         self.inv_a = inv_a
 520         self.imm = imm
 521         self.imm_ok = imm_ok
 522         self.zero_a = zero_a
 523         self.imm_control = (zero_a, imm_ok)
 524         self.rdmaskn = rdmaskn
 525
 526         # Initialize completion flags
 527         self.rd_complete = [False, False]
 528
 529         # trigger operation cycle
 530         yield from self.issue()
 531
 532         # check that the sub-processes completed, before the busy_o cycle ended
 533         for completion in self.rd_complete:
 534             assert completion
 535
 536     def issue(self):
 537         # issue_i starts inactive
 538         yield self.dut.issue_i.eq(0)
 539
 540         for n in range(self.MIN_BUSY_LOW):
 541             yield
 542             # busy_o must remain inactive. It cannot rise on its own.
 543             busy_o = yield self.dut.busy_o
 544             assert not busy_o
 545
 546         # activate issue_i to begin the operation cycle
 547         yield self.dut.issue_i.eq(1)
 548
 549         # at the same time, present the operation
 550         yield self.dut.oper_i.insn_type.eq(self.op)
 551         yield self.dut.oper_i.invert_in.eq(self.inv_a)
 552         yield self.dut.oper_i.imm_data.data.eq(self.imm)
 553         yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok)
 554         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 555         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 556         yield self.dut.rdmaskn.eq(rdmaskn)
 557
 558         # give one cycle for the CompUnit to latch the data
 559         yield
 560
 561         # busy_o must keep being low in this cycle, because issue_i was
 562         # low on the previous cycle.
 563         # It cannot rise on its own.
 564         # Also, busy_o and issue_i must never be active at the same time, ever.
 565         busy_o = yield self.dut.busy_o
 566         assert not busy_o
 567
 568         # Lower issue_i
 569         yield self.dut.issue_i.eq(0)
 570
 571         # deactivate inputs along with issue_i, so we can be sure the data
 572         # was latched at the correct cycle
 573         # note: rdmaskn must be held, while busy_o is active
 574         # TODO: deactivate rdmaskn when the busy_o cycle ends
 575         yield self.dut.oper_i.insn_type.eq(0)
 576         yield self.dut.oper_i.invert_in.eq(0)
 577         yield self.dut.oper_i.imm_data.data.eq(0)
 578         yield self.dut.oper_i.imm_data.ok.eq(0)
 579         yield self.dut.oper_i.zero_a.eq(0)
 580         yield
 581
 582         # wait for busy_o to lower
 583         # timeout after self.MAX_BUSY_WAIT cycles
 584         for n in range(self.MAX_BUSY_WAIT):
 585             # sample busy_o in the current cycle
 586             busy_o = yield self.dut.busy_o
 587             if not busy_o:
 588                 # operation cycle ends when busy_o becomes inactive
 589                 break
 590             yield
 591
 592         # if busy_o is still active, a timeout has occurred
 593         # TODO: Uncomment this, once the test is complete:
 594         # assert not busy_o
 595
 596         if busy_o:
 597             print("If you are reading this, "
 598                   "it's because the above test failed, as expected,\n"
 599                   "with a timeout. It must pass, once the test is complete.")
 600             return
 601
 602         print("If you are reading this, "
 603               "it's because the above test unexpectedly passed.")
 604
 605     def rd(self, rd_idx):
 606         # wait for issue_i to rise
 607         while True:
 608             issue_i = yield self.dut.issue_i
 609             if issue_i:
 610                 break
 611             # issue_i has not risen yet, so rd must keep low
 612             rel = yield self.dut.rd.rel_o[rd_idx]
 613             assert not rel
 614             yield
 615
 616         # we do not want rd to rise on an immediate operand
 617         # if it is immediate, exit the process
 618         # likewise, if the read mask is active
 619         # TODO: don't exit the process, monitor rd instead to ensure it
 620         #       doesn't rise on its own
 621         if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
 622             self.rd_complete[rd_idx] = True
 623             return
 624
 625         # issue_i has risen. rel must rise on the next cycle
 626         rel = yield self.dut.rd.rel_o[rd_idx]
 627         assert not rel
 628
 629         # stall for additional cycles. Check that rel doesn't fall on its own
 630         for n in range(self.RD_GO_DELAY[rd_idx]):
 631             yield
 632             rel = yield self.dut.rd.rel_o[rd_idx]
 633             assert rel
 634
 635         # Before asserting "go", make sure "rel" has risen.
 636         # The use of Settle allows "go" to be set combinatorially,
 637         # rising on the same cycle as "rel".
 638         yield Settle()
 639         rel = yield self.dut.rd.rel_o[rd_idx]
 640         assert rel
 641
 642         # assert go for one cycle, passing along the operand value
 643         yield self.dut.rd.go_i[rd_idx].eq(1)
 644         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
 645         # check that the operand was sent to the alu
 646         # TODO: Properly check the alu protocol
 647         yield Settle()
 648         alu_input = yield self.dut.get_in(rd_idx)
 649         assert alu_input == self.operands[rd_idx]
 650         yield
 651
 652         # rel must keep high, since go was inactive in the last cycle
 653         rel = yield self.dut.rd.rel_o[rd_idx]
 654         assert rel
 655
 656         # finish the go one-clock pulse
 657         yield self.dut.rd.go_i[rd_idx].eq(0)
 658         yield self.dut.src_i[rd_idx].eq(0)
 659         yield
 660
 661         # rel must have gone low in response to go being high
 662         # on the previous cycle
 663         rel = yield self.dut.rd.rel_o[rd_idx]
 664         assert not rel
 665
 666         self.rd_complete[rd_idx] = True
 667
 668         # TODO: check that rel doesn't rise again until the end of the
 669         #       busy_o cycle
 670
 671     def wr(self, wr_idx):
 672         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 673         yield
 674         # TODO: also when dut.wr.go is set, check the output against the
 675         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 676
 677     def run_simulation(self, vcd_name):
 678         m = Module()
 679         m.submodules.cu = self.dut
 680         sim = Simulator(m)
 681         sim.add_clock(1e-6)
 682
 683         sim.add_sync_process(wrap(self.driver()))
 684         sim.add_sync_process(wrap(self.rd(0)))
 685         sim.add_sync_process(wrap(self.rd(1)))
 686         sim.add_sync_process(wrap(self.wr(0)))
 687         sim_writer = sim.write_vcd(vcd_name)
 688         with sim_writer:
 689             sim.run()
 690
 691
 692 def test_compunit_regspec2_fsm():
 693
 694     inspec = [('INT', 'data', '0:15'),
 695               ('INT', 'shift', '0:15')]
 696     outspec = [('INT', 'data', '0:15')]
 697
 698     regspec = (inspec, outspec)
 699
 700     m = Module()
 701     alu = Shifter(8)
 702     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 703     m.submodules.cu = dut
 704
 705     sim = Simulator(m)
 706     sim.add_clock(1e-6)
 707
 708     # create one operand producer for each input port
 709     prod_a = OperandProducer(sim, dut, 0)
 710     prod_b = OperandProducer(sim, dut, 1)
 711     # create an result consumer for the output port
 712     cons = ResultConsumer(sim, dut, 0)
 713     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 714                                                  [prod_a, prod_b],
 715                                                  [cons])))
 716     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 717                                traces=[prod_a.count,
 718                                        prod_b.count,
 719                                        cons.count])
 720     with sim_writer:
 721         sim.run()
 722
 723
 724 def test_compunit_regspec3():
 725
 726     style = {
 727         'in': {'color': 'orange'},
 728         'out': {'color': 'yellow'},
 729     }
 730     traces = [
 731         'clk',
 732         ('operation port', {'color': 'red'}, [
 733             'cu_issue_i', 'cu_busy_o',
 734             {'comment': 'operation'},
 735             ('oper_i_None__insn_type'
 736              + ('' if is_engine_pysim() else '[6:0]'),
 737              {'display': 'insn_type'})]),
 738         ('operand 1 port', 'in', [
 739             ('cu_rd__rel_o[2:0]', {'bit': 2}),
 740             ('cu_rd__go_i[2:0]', {'bit': 2}),
 741             'src1_i[15:0]']),
 742         ('operand 2 port', 'in', [
 743             ('cu_rd__rel_o[2:0]', {'bit': 1}),
 744             ('cu_rd__go_i[2:0]', {'bit': 1}),
 745             'src2_i[15:0]']),
 746         ('operand 3 port', 'in', [
 747             ('cu_rd__rel_o[2:0]', {'bit': 0}),
 748             ('cu_rd__go_i[2:0]', {'bit': 0}),
 749             'src1_i[15:0]']),
 750         ('result port', 'out', [
 751             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 752         ('alu', {'submodule': 'alu'}, [
 753             ('prev port', 'in', [
 754                 'oper_i_None__insn_type', 'i1[15:0]',
 755                 'valid_i', 'ready_o']),
 756             ('next port', 'out', [
 757                 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
 758
 759     write_gtkw("test_compunit_regspec3.gtkw",
 760                "test_compunit_regspec3.vcd",
 761                traces, style,
 762                clk_period=1e-6,
 763                module='top.cu')
 764
 765     inspec = [('INT', 'a', '0:15'),
 766               ('INT', 'b', '0:15'),
 767               ('INT', 'c', '0:15')]
 768     outspec = [('INT', 'o', '0:15')]
 769
 770     regspec = (inspec, outspec)
 771
 772     m = Module()
 773     alu = DummyALU(16)
 774     dut = MultiCompUnit(regspec, alu, CompCROpSubset)
 775     m.submodules.cu = dut
 776
 777     sim = Simulator(m)
 778     sim.add_clock(1e-6)
 779
 780     # create an operation issuer
 781     op = OpSim(dut, sim)
 782     sim.add_sync_process(wrap(scoreboard_sim_dummy(op)))
 783     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 784     with sim_writer:
 785         sim.run()
 786
 787
 788 def test_compunit_regspec1():
 789
 790     style = {
 791         'in': {'color': 'orange'},
 792         'out': {'color': 'yellow'},
 793     }
 794     traces = [
 795         'clk',
 796         ('operation port', {'color': 'red'}, [
 797             'cu_issue_i', 'cu_busy_o',
 798             {'comment': 'operation'},
 799             ('oper_i_None__insn_type'
 800              + ('' if is_engine_pysim() else '[6:0]'),
 801              {'display': 'insn_type'}),
 802             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 803             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 804             ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
 805             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
 806         ('operand 1 port', 'in', [
 807             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 808             ('cu_rd__go_i[1:0]', {'bit': 1}),
 809             'src1_i[15:0]']),
 810         ('operand 2 port', 'in', [
 811             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 812             ('cu_rd__go_i[1:0]', {'bit': 0}),
 813             'src2_i[15:0]']),
 814         ('result port', 'out', [
 815             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 816         ('alu', {'submodule': 'alu'}, [
 817             ('prev port', 'in', [
 818                 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
 819                 'valid_i', 'ready_o']),
 820             ('next port', 'out', [
 821                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
 822         ('debug', {'module': 'top'},
 823             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 824
 825     write_gtkw("test_compunit_regspec1.gtkw",
 826                "test_compunit_regspec1.vcd",
 827                traces, style,
 828                clk_period=1e-6,
 829                module='top.cu')
 830
 831     inspec = [('INT', 'a', '0:15'),
 832               ('INT', 'b', '0:15')]
 833     outspec = [('INT', 'o', '0:15')]
 834
 835     regspec = (inspec, outspec)
 836
 837     m = Module()
 838     alu = ALU(16)
 839     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 840     m.submodules.cu = dut
 841
 842     vl = rtlil.convert(dut, ports=dut.ports())
 843     with open("test_compunit_regspec1.il", "w") as f:
 844         f.write(vl)
 845
 846     sim = Simulator(m)
 847     sim.add_clock(1e-6)
 848
 849     # create an operation issuer
 850     op = OpSim(dut, sim)
 851     sim.add_sync_process(wrap(scoreboard_sim(op)))
 852     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd',
 853                                traces=[op.producers[0].count,
 854                                        op.producers[1].count,
 855                                        op.consumers[0].count])
 856     with sim_writer:
 857         sim.run()
 858
 859     test = CompUnitParallelTest(dut)
 860     test.run_simulation("test_compunit_parallel.vcd")
 861
 862
 863 if __name__ == '__main__':
 864     test_compunit()
 865     test_compunit_fsm()
 866     test_compunit_regspec1()
 867     test_compunit_regspec2_fsm()
 868     test_compunit_regspec3()