src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.fu.cr.cr_input_record import CompCROpSubset
  16 from soc.experiment.alu_hier import ALU, DummyALU
  17 from soc.experiment.compalu_multi import MultiCompUnit
  18 from soc.decoder.power_enums import MicrOp
  19 from nmutil.gtkw import write_gtkw
  20 from nmigen import Module, Signal
  21 from nmigen.cli import rtlil
  22
  23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  25 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  26                                         Passive)
  27
  28
  29 def wrap(process):
  30     def wrapper():
  31         yield from process
  32     return wrapper
  33
  34
  35 class OperandProducer:
  36     """
  37     Produces an operand when requested by the Computation Unit
  38     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  39
  40     Attaches itself to the `dut` operand indexed by `op_index`.
  41
  42     Has a programmable delay between the assertion of `rel_o` and the
  43     `go_i` pulse.
  44
  45     Data is presented only during the cycle in which `go_i` is active.
  46
  47     It adds itself as a passive process to the simulation (`sim` parameter).
  48     Since it is passive, it will not hang the simulation, and does not need a
  49     flag to terminate itself.
  50     """
  51     def __init__(self, sim, dut, op_index):
  52         self.count = Signal(8, name=f"src{op_index + 1}_count")
  53         """ transaction counter"""
  54         # data and handshake signals from the DUT
  55         self.port = dut.src_i[op_index]
  56         self.go_i = dut.rd.go_i[op_index]
  57         self.rel_o = dut.rd.rel_o[op_index]
  58         # transaction parameters, passed via signals
  59         self.delay = Signal(8)
  60         self.data = Signal.like(self.port)
  61         # add ourselves to the simulation process list
  62         sim.add_sync_process(self._process)
  63
  64     def _process(self):
  65         yield Passive()
  66         while True:
  67             # Settle() is needed to give a quick response to
  68             # the zero delay case
  69             yield Settle()
  70             # wait for rel_o to become active
  71             while not (yield self.rel_o):
  72                 yield
  73                 yield Settle()
  74             # read the transaction parameters
  75             delay = (yield self.delay)
  76             data = (yield self.data)
  77             # wait for `delay` cycles
  78             for _ in range(delay):
  79                 yield
  80             # activate go_i and present data, for one cycle
  81             yield self.go_i.eq(1)
  82             yield self.port.eq(data)
  83             yield self.count.eq(self.count + 1)
  84             yield
  85             yield self.go_i.eq(0)
  86             yield self.port.eq(0)
  87
  88     def send(self, data, delay):
  89         """
  90         Schedules the module to send some `data`, counting `delay` cycles after
  91         `rel_i` becomes active.
  92
  93         To be called from the main test-bench process,
  94         it returns in the same cycle.
  95
  96         Communication with the worker process is done by means of
  97         combinatorial simulation-only signals.
  98
  99         """
 100         yield self.data.eq(data)
 101         yield self.delay.eq(delay)
 102
 103
 104 class ResultConsumer:
 105     """
 106     Consumes a result when requested by the Computation Unit
 107     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 108
 109     Attaches itself to the `dut` result indexed by `op_index`.
 110
 111     Has a programmable delay between the assertion of `rel_o` and the
 112     `go_i` pulse.
 113
 114     Data is retrieved only during the cycle in which `go_i` is active.
 115
 116     It adds itself as a passive process to the simulation (`sim` parameter).
 117     Since it is passive, it will not hang the simulation, and does not need a
 118     flag to terminate itself.
 119     """
 120     def __init__(self, sim, dut, op_index):
 121         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 122         """ transaction counter"""
 123         # data and handshake signals from the DUT
 124         self.port = dut.dest[op_index]
 125         self.go_i = dut.wr.go_i[op_index]
 126         self.rel_o = dut.wr.rel_o[op_index]
 127         # transaction parameters, passed via signals
 128         self.delay = Signal(8)
 129         self.expected = Signal.like(self.port)
 130         # add ourselves to the simulation process list
 131         sim.add_sync_process(self._process)
 132
 133     def _process(self):
 134         yield Passive()
 135         while True:
 136             # Settle() is needed to give a quick response to
 137             # the zero delay case
 138             yield Settle()
 139             # wait for rel_o to become active
 140             while not (yield self.rel_o):
 141                 yield
 142                 yield Settle()
 143             # read the transaction parameters
 144             delay = (yield self.delay)
 145             expected = (yield self.expected)
 146             # wait for `delay` cycles
 147             for _ in range(delay):
 148                 yield
 149             # activate go_i for one cycle
 150             yield self.go_i.eq(1)
 151             yield self.count.eq(self.count + 1)
 152             yield
 153             # check received data against the expected value
 154             result = (yield self.port)
 155             assert result == expected,\
 156                 f"expected {expected}, received {result}"
 157             yield self.go_i.eq(0)
 158             yield self.port.eq(0)
 159
 160     def receive(self, expected, delay):
 161         """
 162         Schedules the module to receive some result,
 163         counting `delay` cycles after `rel_i` becomes active.
 164         As 'go_i' goes active, check the result with `expected`.
 165
 166         To be called from the main test-bench process,
 167         it returns in the same cycle.
 168
 169         Communication with the worker process is done by means of
 170         combinatorial simulation-only signals.
 171         """
 172         yield self.expected.eq(expected)
 173         yield self.delay.eq(delay)
 174
 175
 176 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 177     yield dut.issue_i.eq(0)
 178     yield
 179     yield dut.src_i[0].eq(a)
 180     yield dut.src_i[1].eq(b)
 181     yield dut.oper_i.insn_type.eq(op)
 182     yield dut.oper_i.invert_in.eq(inv_a)
 183     yield dut.oper_i.imm_data.data.eq(imm)
 184     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 185     yield dut.oper_i.zero_a.eq(zero_a)
 186     yield dut.issue_i.eq(1)
 187     yield
 188     yield dut.issue_i.eq(0)
 189     yield
 190     if not imm_ok or not zero_a:
 191         yield dut.rd.go_i.eq(0b11)
 192         while True:
 193             yield
 194             rd_rel_o = yield dut.rd.rel_o
 195             print("rd_rel", rd_rel_o)
 196             if rd_rel_o:
 197                 break
 198         yield dut.rd.go_i.eq(0)
 199     else:
 200         print("no go rd")
 201
 202     if len(dut.src_i) == 3:
 203         yield dut.rd.go_i.eq(0b100)
 204         while True:
 205             yield
 206             rd_rel_o = yield dut.rd.rel_o
 207             print("rd_rel", rd_rel_o)
 208             if rd_rel_o:
 209                 break
 210         yield dut.rd.go_i.eq(0)
 211     else:
 212         print("no 3rd rd")
 213
 214     req_rel_o = yield dut.wr.rel_o
 215     result = yield dut.data_o
 216     print("req_rel", req_rel_o, result)
 217     while True:
 218         req_rel_o = yield dut.wr.rel_o
 219         result = yield dut.data_o
 220         print("req_rel", req_rel_o, result)
 221         if req_rel_o:
 222             break
 223         yield
 224     yield dut.wr.go_i[0].eq(1)
 225     yield Settle()
 226     result = yield dut.data_o
 227     yield
 228     print("result", result)
 229     yield dut.wr.go_i[0].eq(0)
 230     yield
 231     return result
 232
 233
 234 def scoreboard_sim_fsm(dut, producers, consumers):
 235
 236     # stores the operation count
 237     op_count = 0
 238
 239     def op_sim_fsm(a, b, direction, expected, delays):
 240         print("op_sim_fsm", a, b, direction, expected)
 241         yield dut.issue_i.eq(0)
 242         yield
 243         # forward data and delays to the producers and consumers
 244         yield from producers[0].send(a, delays[0])
 245         yield from producers[1].send(b, delays[1])
 246         yield from consumers[0].receive(expected, delays[2])
 247         # submit operation, and assert issue_i for one cycle
 248         yield dut.oper_i.sdir.eq(direction)
 249         yield dut.issue_i.eq(1)
 250         yield
 251         yield dut.issue_i.eq(0)
 252         # wait for busy to be negated
 253         yield Settle()
 254         while (yield dut.busy_o):
 255             yield
 256             yield Settle()
 257         # update the operation count
 258         nonlocal op_count
 259         op_count = (op_count + 1) & 255
 260         # check that producers and consumers have the same count
 261         # this assures that no data was left unused or was lost
 262         assert (yield producers[0].count) == op_count
 263         assert (yield producers[1].count) == op_count
 264         assert (yield consumers[0].count) == op_count
 265
 266     # 13 >> 2 = 3
 267     # operand 1 arrives immediately
 268     # operand 2 arrives after operand 1
 269     # write data is accepted immediately
 270     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 271     # 3 << 4 = 48
 272     # operand 2 arrives immediately
 273     # operand 1 arrives after operand 2
 274     # write data is accepted after some delay
 275     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 276     # 21 << 0 = 21
 277     # operands 1 and 2 arrive at the same time
 278     # write data is accepted after some delay
 279     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 280
 281
 282 def scoreboard_sim_dummy(op):
 283     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 284                         src_delays=[0, 2, 1], dest_delays=[0])
 285     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 286                         src_delays=[2, 1, 0], dest_delays=[2])
 287     # test all combinations of masked input ports
 288     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [0],
 289                         rdmaskn=[1, 0, 0],
 290                         src_delays=[0, 2, 1], dest_delays=[0])
 291     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 292                         rdmaskn=[0, 1, 0],
 293                         src_delays=[2, 1, 0], dest_delays=[2])
 294     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 295                         rdmaskn=[0, 0, 1],
 296                         src_delays=[2, 1, 0], dest_delays=[2])
 297     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 298                         rdmaskn=[0, 1, 1],
 299                         src_delays=[2, 1, 0], dest_delays=[2])
 300     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 301                         rdmaskn=[1, 1, 0],
 302                         src_delays=[2, 1, 0], dest_delays=[2])
 303     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 304                         rdmaskn=[1, 1, 1],
 305                         src_delays=[2, 1, 0], dest_delays=[2])
 306
 307
 308 class OpSim:
 309     """ALU Operation issuer
 310
 311     Issues operations to the DUT"""
 312     def __init__(self, dut, sim):
 313         self.op_count = 0
 314         self.zero_a_count = 0
 315         self.imm_ok_count = 0
 316         self.rdmaskn_count = [0] * len(dut.src_i)
 317         self.wrmask_count = [0] * len(dut.dest)
 318         self.dut = dut
 319         # create one operand producer for each input port
 320         self.producers = list()
 321         for i in range(len(dut.src_i)):
 322             self.producers.append(OperandProducer(sim, dut, i))
 323         # create one result consumer for each output port
 324         self.consumers = list()
 325         for i in range(len(dut.dest)):
 326             self.consumers.append(ResultConsumer(sim, dut, i))
 327
 328     def issue(self, src_i, op, expected, src_delays, dest_delays,
 329               inv_a=0, imm=0, imm_ok=0, zero_a=0, rc=0,
 330               rdmaskn=None, wrmask=None):
 331         """Executes the issue operation"""
 332         dut = self.dut
 333         producers = self.producers
 334         consumers = self.consumers
 335         if rdmaskn is None:
 336             rdmaskn = [0] * len(src_i)
 337         if wrmask is None:
 338             wrmask = [0] * len(expected)
 339         yield dut.issue_i.eq(0)
 340         yield
 341         # forward data and delays to the producers and consumers
 342         # first, send special cases (with zero_a and/or imm_ok)
 343         if not zero_a:
 344             yield from producers[0].send(src_i[0], src_delays[0])
 345         if not imm_ok:
 346             yield from producers[1].send(src_i[1], src_delays[1])
 347         # then, send the rest (if any)
 348         for i in range(2, len(producers)):
 349             yield from producers[i].send(src_i[i], src_delays[i])
 350         for i in range(len(consumers)):
 351             yield from consumers[i].receive(expected[i], dest_delays[i])
 352         # submit operation, and assert issue_i for one cycle
 353         yield dut.oper_i.insn_type.eq(op)
 354         if hasattr(dut.oper_i, "invert_in"):
 355             yield dut.oper_i.invert_in.eq(inv_a)
 356         if hasattr(dut.oper_i, "imm_data"):
 357             yield dut.oper_i.imm_data.data.eq(imm)
 358             yield dut.oper_i.imm_data.ok.eq(imm_ok)
 359         if hasattr(dut.oper_i, "zero_a"):
 360             yield dut.oper_i.zero_a.eq(zero_a)
 361         if hasattr(dut.oper_i, "rc"):
 362             yield dut.oper_i.rc.rc.eq(rc)
 363         if hasattr(dut, "rdmaskn"):
 364             rdmaskn_bits = 0
 365             for i in range(len(rdmaskn)):
 366                 rdmaskn_bits |= rdmaskn[i] << i
 367             yield dut.rdmaskn.eq(rdmaskn_bits)
 368         yield dut.issue_i.eq(1)
 369         yield
 370         yield dut.issue_i.eq(0)
 371         # deactivate decoder inputs along with issue_i, so we can be sure they
 372         # were latched at the correct cycle
 373         # note: rdmaskn is not latched, and must be held as long as
 374         # busy_o is active
 375         # See: https://bugs.libre-soc.org/show_bug.cgi?id=336#c44
 376         yield self.dut.oper_i.insn_type.eq(0)
 377         if hasattr(dut.oper_i, "invert_in"):
 378             yield self.dut.oper_i.invert_in.eq(0)
 379         if hasattr(dut.oper_i, "imm_data"):
 380             yield self.dut.oper_i.imm_data.data.eq(0)
 381             yield self.dut.oper_i.imm_data.ok.eq(0)
 382         if hasattr(dut.oper_i, "zero_a"):
 383             yield self.dut.oper_i.zero_a.eq(0)
 384         if hasattr(dut.oper_i, "rc"):
 385             yield dut.oper_i.rc.rc.eq(0)
 386         # wait for busy to be negated
 387         yield Settle()
 388         while (yield dut.busy_o):
 389             yield
 390             yield Settle()
 391         # now, deactivate rdmaskn
 392         if hasattr(dut, "rdmaskn"):
 393             yield dut.rdmaskn.eq(0)
 394         # update the operation count
 395         self.op_count = (self.op_count + 1) & 255
 396         # On zero_a, imm_ok and rdmaskn executions, the producer counters will
 397         # fall behind. But, by summing the following counts, the invariant is
 398         # preserved.
 399         if zero_a and not rdmaskn[0]:
 400             self.zero_a_count += 1
 401         if imm_ok and not rdmaskn[1]:
 402             self.imm_ok_count += 1
 403         for i in range(len(rdmaskn)):
 404             if rdmaskn[i]:
 405                 self.rdmaskn_count[i] += 1
 406         for i in range(len(wrmask)):
 407             if wrmask[i]:
 408                 self.wrmask_count[i] += 1
 409         # check that producers and consumers have the same count
 410         # this assures that no data was left unused or was lost
 411         # first, check special cases (zero_a and imm_ok)
 412         port_a_cnt = \
 413             (yield producers[0].count) \
 414             + self.zero_a_count \
 415             + self.rdmaskn_count[0]
 416         port_b_cnt = \
 417             (yield producers[1].count) \
 418             + self.imm_ok_count \
 419             + self.rdmaskn_count[1]
 420         assert port_a_cnt == self.op_count
 421         assert port_b_cnt == self.op_count
 422         # then, check the rest (if any)
 423         for i in range(2, len(producers)):
 424             port_cnt = (yield producers[i].count) + self.rdmaskn_count[i]
 425             assert port_cnt == self.op_count
 426         # check write counter
 427         for i in range(len(consumers)):
 428             port_cnt = (yield consumers[i].count) + self.wrmask_count[i]
 429             assert port_cnt == self.op_count
 430
 431
 432 def scoreboard_sim(op):
 433     # the following tests cases have rc=0, so no CR output is expected
 434     # zero (no) input operands test
 435     # 0 + 8 = 8
 436     yield from op.issue([5, 2], MicrOp.OP_ADD, [8, 0],
 437                         zero_a=1, imm=8, imm_ok=1,
 438                         wrmask=[0, 1],
 439                         src_delays=[0, 2], dest_delays=[0, 0])
 440     # 5 + 8 = 13
 441     yield from op.issue([5, 2], MicrOp.OP_ADD, [13, 0],
 442                         inv_a=0, imm=8, imm_ok=1,
 443                         wrmask=[0, 1],
 444                         src_delays=[2, 0], dest_delays=[2, 0])
 445     # 5 + 2 = 7
 446     yield from op.issue([5, 2], MicrOp.OP_ADD, [7, 0],
 447                         wrmask=[0, 1],
 448                         src_delays=[1, 1], dest_delays=[1, 0])
 449     # (-6) + 2 = (-4)
 450     yield from op.issue([5, 2], MicrOp.OP_ADD, [65532, 0],
 451                         inv_a=1,
 452                         wrmask=[0, 1],
 453                         src_delays=[1, 2], dest_delays=[0, 0])
 454     # 0 + 2 = 2
 455     yield from op.issue([5, 2], MicrOp.OP_ADD, [2, 0],
 456                         zero_a=1,
 457                         wrmask=[0, 1],
 458                         src_delays=[2, 0], dest_delays=[1, 0])
 459
 460     # test combinatorial zero-delay operation
 461     # In the test ALU, any operation other than ADD, MUL, EXTS or SHR
 462     # is zero-delay, and do a subtraction.
 463     # 5 - 2 = 3
 464     yield from op.issue([5, 2], MicrOp.OP_CMP, [3, 0],
 465                         wrmask=[0, 1],
 466                         src_delays=[0, 1], dest_delays=[2, 0])
 467     # test all combinations of masked input ports
 468     # NOP does not make any request nor response
 469     yield from op.issue([5, 2], MicrOp.OP_NOP, [0, 0],
 470                         rdmaskn=[1, 1], wrmask=[1, 1],
 471                         src_delays=[1, 2], dest_delays=[1, 0])
 472     # sign_extend(0x80) = 0xFF80
 473     yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80, 0],
 474                         rdmaskn=[0, 1], wrmask=[0, 1],
 475                         src_delays=[2, 1], dest_delays=[0, 0])
 476     # sign_extend(0x80) = 0xFF80
 477     yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80, 0],
 478                         rdmaskn=[1, 0], wrmask=[0, 1],
 479                         src_delays=[1, 2], dest_delays=[1, 0])
 480     # test with rc=1, so expect results on the CR output port
 481     # 5 + 2 = 7
 482     # 7 > 0 => CR = 0b100
 483     yield from op.issue([5, 2], MicrOp.OP_ADD, [7, 0b100],
 484                         rc=1,
 485                         src_delays=[1, 1], dest_delays=[1, 0])
 486     # sign_extend(0x80) = 0xFF80
 487     # -128 < 0 => CR = 0b010
 488     yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80, 0b010],
 489                         rc=1, rdmaskn=[0, 1],
 490                         src_delays=[2, 1], dest_delays=[0, 2])
 491     # 5 - 5 = 0
 492     # 0 == 0 => CR = 0b001
 493     yield from op.issue([5, 2], MicrOp.OP_CMP, [0, 0b001],
 494                         imm=5, imm_ok=1, rc=1,
 495                         src_delays=[0, 1], dest_delays=[2, 1])
 496
 497
 498 def test_compunit_fsm():
 499     style = {
 500         'in': {'color': 'orange'},
 501         'out': {'color': 'yellow'},
 502     }
 503     traces = [
 504         'clk',
 505         ('operation port', {'color': 'red'}, [
 506             'cu_issue_i', 'cu_busy_o',
 507             {'comment': 'operation'},
 508             'oper_i_None__sdir']),
 509         ('operand 1 port', 'in', [
 510             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 511             ('cu_rd__go_i[1:0]', {'bit': 1}),
 512             'src1_i[7:0]']),
 513         ('operand 2 port', 'in', [
 514             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 515             ('cu_rd__go_i[1:0]', {'bit': 0}),
 516             'src2_i[7:0]']),
 517         ('result port', 'out', [
 518             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 519         ('alu', {'submodule': 'alu'}, [
 520             ('prev port', 'in', [
 521                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 522                 ({'submodule': 'p'},
 523                     ['p_valid_i', 'p_ready_o'])]),
 524             ('next port', 'out', [
 525                 'n_data_o[7:0]',
 526                 ({'submodule': 'n'},
 527                     ['n_valid_o', 'n_ready_i'])])]),
 528         ('debug', {'module': 'top'},
 529             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 530
 531     write_gtkw(
 532         "test_compunit_fsm1.gtkw",
 533         "test_compunit_fsm1.vcd",
 534         traces, style,
 535         module='top.cu'
 536     )
 537     m = Module()
 538     alu = Shifter(8)
 539     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 540     m.submodules.cu = dut
 541
 542     vl = rtlil.convert(dut, ports=dut.ports())
 543     with open("test_compunit_fsm1.il", "w") as f:
 544         f.write(vl)
 545
 546     sim = Simulator(m)
 547     sim.add_clock(1e-6)
 548
 549     # create one operand producer for each input port
 550     prod_a = OperandProducer(sim, dut, 0)
 551     prod_b = OperandProducer(sim, dut, 1)
 552     # create an result consumer for the output port
 553     cons = ResultConsumer(sim, dut, 0)
 554     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 555                                                  [prod_a, prod_b],
 556                                                  [cons])))
 557     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 558                                traces=[prod_a.count,
 559                                        prod_b.count,
 560                                        cons.count])
 561     with sim_writer:
 562         sim.run()
 563
 564
 565 def test_compunit():
 566
 567     m = Module()
 568     alu = ALU(16)
 569     dut = MultiCompUnit(16, alu, CompALUOpSubset, n_dst=2)
 570     m.submodules.cu = dut
 571
 572     vl = rtlil.convert(dut, ports=dut.ports())
 573     with open("test_compunit1.il", "w") as f:
 574         f.write(vl)
 575
 576     sim = Simulator(m)
 577     sim.add_clock(1e-6)
 578
 579     # create an operation issuer
 580     op = OpSim(dut, sim)
 581     sim.add_sync_process(wrap(scoreboard_sim(op)))
 582     sim_writer = sim.write_vcd('test_compunit1.vcd')
 583     with sim_writer:
 584         sim.run()
 585
 586
 587 def test_compunit_regspec2_fsm():
 588
 589     inspec = [('INT', 'data', '0:15'),
 590               ('INT', 'shift', '0:15')]
 591     outspec = [('INT', 'data', '0:15')]
 592
 593     regspec = (inspec, outspec)
 594
 595     m = Module()
 596     alu = Shifter(8)
 597     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 598     m.submodules.cu = dut
 599
 600     sim = Simulator(m)
 601     sim.add_clock(1e-6)
 602
 603     # create one operand producer for each input port
 604     prod_a = OperandProducer(sim, dut, 0)
 605     prod_b = OperandProducer(sim, dut, 1)
 606     # create an result consumer for the output port
 607     cons = ResultConsumer(sim, dut, 0)
 608     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 609                                                  [prod_a, prod_b],
 610                                                  [cons])))
 611     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 612                                traces=[prod_a.count,
 613                                        prod_b.count,
 614                                        cons.count])
 615     with sim_writer:
 616         sim.run()
 617
 618
 619 def test_compunit_regspec3():
 620
 621     style = {
 622         'in': {'color': 'orange'},
 623         'out': {'color': 'yellow'},
 624     }
 625     traces = [
 626         'clk',
 627         ('operation port', {'color': 'red'}, [
 628             'cu_issue_i', 'cu_busy_o',
 629             {'comment': 'operation'},
 630             ('oper_i_None__insn_type'
 631              + ('' if is_engine_pysim() else '[6:0]'),
 632              {'display': 'insn_type'})]),
 633         ('operand 1 port', 'in', [
 634             ('cu_rdmaskn_i[2:0]', {'bit': 2}),
 635             ('cu_rd__rel_o[2:0]', {'bit': 2}),
 636             ('cu_rd__go_i[2:0]', {'bit': 2}),
 637             'src1_i[15:0]']),
 638         ('operand 2 port', 'in', [
 639             ('cu_rdmaskn_i[2:0]', {'bit': 1}),
 640             ('cu_rd__rel_o[2:0]', {'bit': 1}),
 641             ('cu_rd__go_i[2:0]', {'bit': 1}),
 642             'src2_i[15:0]']),
 643         ('operand 3 port', 'in', [
 644             ('cu_rdmaskn_i[2:0]', {'bit': 0}),
 645             ('cu_rd__rel_o[2:0]', {'bit': 0}),
 646             ('cu_rd__go_i[2:0]', {'bit': 0}),
 647             'src1_i[15:0]']),
 648         ('result port', 'out', [
 649             'cu_wrmask_o', 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 650         ('alu', {'submodule': 'alu'}, [
 651             ('prev port', 'in', [
 652                 'oper_i_None__insn_type', 'i1[15:0]',
 653                 'valid_i', 'ready_o']),
 654             ('next port', 'out', [
 655                 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
 656
 657     write_gtkw("test_compunit_regspec3.gtkw",
 658                "test_compunit_regspec3.vcd",
 659                traces, style,
 660                clk_period=1e-6,
 661                module='top.cu')
 662
 663     inspec = [('INT', 'a', '0:15'),
 664               ('INT', 'b', '0:15'),
 665               ('INT', 'c', '0:15')]
 666     outspec = [('INT', 'o', '0:15')]
 667
 668     regspec = (inspec, outspec)
 669
 670     m = Module()
 671     alu = DummyALU(16)
 672     dut = MultiCompUnit(regspec, alu, CompCROpSubset)
 673     m.submodules.cu = dut
 674
 675     sim = Simulator(m)
 676     sim.add_clock(1e-6)
 677
 678     # create an operation issuer
 679     op = OpSim(dut, sim)
 680     sim.add_sync_process(wrap(scoreboard_sim_dummy(op)))
 681     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 682     with sim_writer:
 683         sim.run()
 684
 685
 686 def test_compunit_regspec1():
 687
 688     style = {
 689         'in': {'color': 'orange'},
 690         'out': {'color': 'yellow'},
 691     }
 692     traces = [
 693         'clk',
 694         ('operation port', {'color': 'red'}, [
 695             'cu_issue_i', 'cu_busy_o',
 696             {'comment': 'operation'},
 697             ('oper_i_None__insn_type'
 698              + ('' if is_engine_pysim() else '[6:0]'),
 699              {'display': 'insn_type'}),
 700             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 701             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 702             ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
 703             ('oper_i_None__zero_a', {'display': 'zero_a'}),
 704             ('oper_i_None__rc__rc', {'display': 'rc'})]),
 705         ('operand 1 port', 'in', [
 706             ('cu_rdmaskn_i[1:0]', {'bit': 1}),
 707             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 708             ('cu_rd__go_i[1:0]', {'bit': 1}),
 709             'src1_i[15:0]']),
 710         ('operand 2 port', 'in', [
 711             ('cu_rdmaskn_i[1:0]', {'bit': 0}),
 712             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 713             ('cu_rd__go_i[1:0]', {'bit': 0}),
 714             'src2_i[15:0]']),
 715         ('result port', 'out', [
 716             ('cu_wrmask_o[1:0]', {'bit': 1}),
 717             ('cu_wr__rel_o[1:0]', {'bit': 1}),
 718             ('cu_wr__go_i[1:0]', {'bit': 1}),
 719             'dest1_o[15:0]']),
 720         ('cr port', 'out', [
 721             ('cu_wrmask_o[1:0]', {'bit': 0}),
 722             ('cu_wr__rel_o[1:0]', {'bit': 0}),
 723             ('cu_wr__go_i[1:0]', {'bit': 0}),
 724             'dest2_o[15:0]']),
 725         ('alu', {'submodule': 'alu'}, [
 726             ('prev port', 'in', [
 727                 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
 728                 'valid_i', 'ready_o']),
 729             ('next port', 'out', [
 730                 'alu_o[15:0]', 'valid_o', 'ready_i',
 731                 'alu_o_ok', 'alu_cr_ok'])]),
 732         ('debug', {'module': 'top'},
 733             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 734
 735     write_gtkw("test_compunit_regspec1.gtkw",
 736                "test_compunit_regspec1.vcd",
 737                traces, style,
 738                clk_period=1e-6,
 739                module='top.cu')
 740
 741     inspec = [('INT', 'a', '0:15'),
 742               ('INT', 'b', '0:15')]
 743     outspec = [('INT', 'o', '0:15'),
 744                ('INT', 'cr', '0:15')]
 745
 746     regspec = (inspec, outspec)
 747
 748     m = Module()
 749     alu = ALU(16)
 750     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 751     m.submodules.cu = dut
 752
 753     vl = rtlil.convert(dut, ports=dut.ports())
 754     with open("test_compunit_regspec1.il", "w") as f:
 755         f.write(vl)
 756
 757     sim = Simulator(m)
 758     sim.add_clock(1e-6)
 759
 760     # create an operation issuer
 761     op = OpSim(dut, sim)
 762     sim.add_sync_process(wrap(scoreboard_sim(op)))
 763     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd',
 764                                traces=[op.producers[0].count,
 765                                        op.producers[1].count,
 766                                        op.consumers[0].count])
 767     with sim_writer:
 768         sim.run()
 769
 770
 771 if __name__ == '__main__':
 772     test_compunit()
 773     test_compunit_fsm()
 774     test_compunit_regspec1()
 775     test_compunit_regspec2_fsm()
 776     test_compunit_regspec3()