src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.fu.cr.cr_input_record import CompCROpSubset
  16 from soc.experiment.alu_hier import ALU, DummyALU
  17 from soc.experiment.compalu_multi import MultiCompUnit
  18 from soc.decoder.power_enums import MicrOp
  19 from nmutil.gtkw import write_gtkw
  20 from nmigen import Module, Signal
  21 from nmigen.cli import rtlil
  22
  23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  25 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  26                                         Passive)
  27
  28
  29 def wrap(process):
  30     def wrapper():
  31         yield from process
  32     return wrapper
  33
  34
  35 class OperandProducer:
  36     """
  37     Produces an operand when requested by the Computation Unit
  38     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  39
  40     Attaches itself to the `dut` operand indexed by `op_index`.
  41
  42     Has a programmable delay between the assertion of `rel_o` and the
  43     `go_i` pulse.
  44
  45     Data is presented only during the cycle in which `go_i` is active.
  46
  47     It adds itself as a passive process to the simulation (`sim` parameter).
  48     Since it is passive, it will not hang the simulation, and does not need a
  49     flag to terminate itself.
  50     """
  51     def __init__(self, sim, dut, op_index):
  52         self.count = Signal(8, name=f"src{op_index + 1}_count")
  53         """ transaction counter"""
  54         # data and handshake signals from the DUT
  55         self.port = dut.src_i[op_index]
  56         self.go_i = dut.rd.go_i[op_index]
  57         self.rel_o = dut.rd.rel_o[op_index]
  58         # transaction parameters, passed via signals
  59         self.delay = Signal(8)
  60         self.data = Signal.like(self.port)
  61         # add ourselves to the simulation process list
  62         sim.add_sync_process(self._process)
  63
  64     def _process(self):
  65         yield Passive()
  66         while True:
  67             # Settle() is needed to give a quick response to
  68             # the zero delay case
  69             yield Settle()
  70             # wait for rel_o to become active
  71             while not (yield self.rel_o):
  72                 yield
  73                 yield Settle()
  74             # read the transaction parameters
  75             delay = (yield self.delay)
  76             data = (yield self.data)
  77             # wait for `delay` cycles
  78             for _ in range(delay):
  79                 yield
  80             # activate go_i and present data, for one cycle
  81             yield self.go_i.eq(1)
  82             yield self.port.eq(data)
  83             yield self.count.eq(self.count + 1)
  84             yield
  85             yield self.go_i.eq(0)
  86             yield self.port.eq(0)
  87
  88     def send(self, data, delay):
  89         """
  90         Schedules the module to send some `data`, counting `delay` cycles after
  91         `rel_i` becomes active.
  92
  93         To be called from the main test-bench process,
  94         it returns in the same cycle.
  95
  96         Communication with the worker process is done by means of
  97         combinatorial simulation-only signals.
  98
  99         """
 100         yield self.data.eq(data)
 101         yield self.delay.eq(delay)
 102
 103
 104 class ResultConsumer:
 105     """
 106     Consumes a result when requested by the Computation Unit
 107     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 108
 109     Attaches itself to the `dut` result indexed by `op_index`.
 110
 111     Has a programmable delay between the assertion of `rel_o` and the
 112     `go_i` pulse.
 113
 114     Data is retrieved only during the cycle in which `go_i` is active.
 115
 116     It adds itself as a passive process to the simulation (`sim` parameter).
 117     Since it is passive, it will not hang the simulation, and does not need a
 118     flag to terminate itself.
 119     """
 120     def __init__(self, sim, dut, op_index):
 121         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 122         """ transaction counter"""
 123         # data and handshake signals from the DUT
 124         self.port = dut.dest[op_index]
 125         self.go_i = dut.wr.go_i[op_index]
 126         self.rel_o = dut.wr.rel_o[op_index]
 127         # transaction parameters, passed via signals
 128         self.delay = Signal(8)
 129         self.expected = Signal.like(self.port)
 130         # add ourselves to the simulation process list
 131         sim.add_sync_process(self._process)
 132
 133     def _process(self):
 134         yield Passive()
 135         while True:
 136             # Settle() is needed to give a quick response to
 137             # the zero delay case
 138             yield Settle()
 139             # wait for rel_o to become active
 140             while not (yield self.rel_o):
 141                 yield
 142                 yield Settle()
 143             # read the transaction parameters
 144             delay = (yield self.delay)
 145             expected = (yield self.expected)
 146             # wait for `delay` cycles
 147             for _ in range(delay):
 148                 yield
 149             # activate go_i for one cycle
 150             yield self.go_i.eq(1)
 151             yield self.count.eq(self.count + 1)
 152             yield
 153             # check received data against the expected value
 154             result = (yield self.port)
 155             assert result == expected,\
 156                 f"expected {expected}, received {result}"
 157             yield self.go_i.eq(0)
 158             yield self.port.eq(0)
 159
 160     def receive(self, expected, delay):
 161         """
 162         Schedules the module to receive some result,
 163         counting `delay` cycles after `rel_i` becomes active.
 164         As 'go_i' goes active, check the result with `expected`.
 165
 166         To be called from the main test-bench process,
 167         it returns in the same cycle.
 168
 169         Communication with the worker process is done by means of
 170         combinatorial simulation-only signals.
 171         """
 172         yield self.expected.eq(expected)
 173         yield self.delay.eq(delay)
 174
 175
 176 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 177     yield dut.issue_i.eq(0)
 178     yield
 179     yield dut.src_i[0].eq(a)
 180     yield dut.src_i[1].eq(b)
 181     yield dut.oper_i.insn_type.eq(op)
 182     yield dut.oper_i.invert_in.eq(inv_a)
 183     yield dut.oper_i.imm_data.data.eq(imm)
 184     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 185     yield dut.oper_i.zero_a.eq(zero_a)
 186     yield dut.issue_i.eq(1)
 187     yield
 188     yield dut.issue_i.eq(0)
 189     yield
 190     if not imm_ok or not zero_a:
 191         yield dut.rd.go_i.eq(0b11)
 192         while True:
 193             yield
 194             rd_rel_o = yield dut.rd.rel_o
 195             print("rd_rel", rd_rel_o)
 196             if rd_rel_o:
 197                 break
 198         yield dut.rd.go_i.eq(0)
 199     else:
 200         print("no go rd")
 201
 202     if len(dut.src_i) == 3:
 203         yield dut.rd.go_i.eq(0b100)
 204         while True:
 205             yield
 206             rd_rel_o = yield dut.rd.rel_o
 207             print("rd_rel", rd_rel_o)
 208             if rd_rel_o:
 209                 break
 210         yield dut.rd.go_i.eq(0)
 211     else:
 212         print("no 3rd rd")
 213
 214     req_rel_o = yield dut.wr.rel_o
 215     result = yield dut.data_o
 216     print("req_rel", req_rel_o, result)
 217     while True:
 218         req_rel_o = yield dut.wr.rel_o
 219         result = yield dut.data_o
 220         print("req_rel", req_rel_o, result)
 221         if req_rel_o:
 222             break
 223         yield
 224     yield dut.wr.go_i[0].eq(1)
 225     yield Settle()
 226     result = yield dut.data_o
 227     yield
 228     print("result", result)
 229     yield dut.wr.go_i[0].eq(0)
 230     yield
 231     return result
 232
 233
 234 def scoreboard_sim_fsm(dut, producers, consumers):
 235
 236     # stores the operation count
 237     op_count = 0
 238
 239     def op_sim_fsm(a, b, direction, expected, delays):
 240         print("op_sim_fsm", a, b, direction, expected)
 241         yield dut.issue_i.eq(0)
 242         yield
 243         # forward data and delays to the producers and consumers
 244         yield from producers[0].send(a, delays[0])
 245         yield from producers[1].send(b, delays[1])
 246         yield from consumers[0].receive(expected, delays[2])
 247         # submit operation, and assert issue_i for one cycle
 248         yield dut.oper_i.sdir.eq(direction)
 249         yield dut.issue_i.eq(1)
 250         yield
 251         yield dut.issue_i.eq(0)
 252         # wait for busy to be negated
 253         yield Settle()
 254         while (yield dut.busy_o):
 255             yield
 256             yield Settle()
 257         # update the operation count
 258         nonlocal op_count
 259         op_count = (op_count + 1) & 255
 260         # check that producers and consumers have the same count
 261         # this assures that no data was left unused or was lost
 262         assert (yield producers[0].count) == op_count
 263         assert (yield producers[1].count) == op_count
 264         assert (yield consumers[0].count) == op_count
 265
 266     # 13 >> 2 = 3
 267     # operand 1 arrives immediately
 268     # operand 2 arrives after operand 1
 269     # write data is accepted immediately
 270     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 271     # 3 << 4 = 48
 272     # operand 2 arrives immediately
 273     # operand 1 arrives after operand 2
 274     # write data is accepted after some delay
 275     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 276     # 21 << 0 = 21
 277     # operands 1 and 2 arrive at the same time
 278     # write data is accepted after some delay
 279     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 280
 281
 282 def scoreboard_sim_dummy(op):
 283     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 284                         src_delays=[0, 2, 1], dest_delays=[0])
 285     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 286                         src_delays=[2, 1, 0], dest_delays=[2])
 287     # test all combinations of masked input ports
 288     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [0],
 289                         rdmaskn=[1, 0, 0],
 290                         src_delays=[0, 2, 1], dest_delays=[0])
 291     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 292                         rdmaskn=[0, 1, 0],
 293                         src_delays=[2, 1, 0], dest_delays=[2])
 294     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 295                         rdmaskn=[0, 0, 1],
 296                         src_delays=[2, 1, 0], dest_delays=[2])
 297     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 298                         rdmaskn=[0, 1, 1],
 299                         src_delays=[2, 1, 0], dest_delays=[2])
 300     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 301                         rdmaskn=[1, 1, 0],
 302                         src_delays=[2, 1, 0], dest_delays=[2])
 303     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 304                         rdmaskn=[1, 1, 1],
 305                         src_delays=[2, 1, 0], dest_delays=[2])
 306
 307
 308 class OpSim:
 309     """ALU Operation issuer
 310
 311     Issues operations to the DUT"""
 312     def __init__(self, dut, sim):
 313         self.op_count = 0
 314         self.zero_a_count = 0
 315         self.imm_ok_count = 0
 316         self.rdmaskn_count = [0] * len(dut.src_i)
 317         self.wrmask_count = [0] * len(dut.dest)
 318         self.dut = dut
 319         # create one operand producer for each input port
 320         self.producers = list()
 321         for i in range(len(dut.src_i)):
 322             self.producers.append(OperandProducer(sim, dut, i))
 323         # create one result consumer for each output port
 324         self.consumers = list()
 325         for i in range(len(dut.dest)):
 326             self.consumers.append(ResultConsumer(sim, dut, i))
 327
 328     def issue(self, src_i, op, expected, src_delays, dest_delays,
 329               inv_a=0, imm=0, imm_ok=0, zero_a=0,
 330               rdmaskn=None, wrmask=None):
 331         """Executes the issue operation"""
 332         dut = self.dut
 333         producers = self.producers
 334         consumers = self.consumers
 335         if rdmaskn is None:
 336             rdmaskn = [0] * len(src_i)
 337         if wrmask is None:
 338             wrmask = [0] * len(expected)
 339         yield dut.issue_i.eq(0)
 340         yield
 341         # forward data and delays to the producers and consumers
 342         # first, send special cases (with zero_a and/or imm_ok)
 343         if not zero_a:
 344             yield from producers[0].send(src_i[0], src_delays[0])
 345         if not imm_ok:
 346             yield from producers[1].send(src_i[1], src_delays[1])
 347         # then, send the rest (if any)
 348         for i in range(2, len(producers)):
 349             yield from producers[i].send(src_i[i], src_delays[i])
 350         for i in range(len(consumers)):
 351             yield from consumers[i].receive(expected[i], dest_delays[i])
 352         # submit operation, and assert issue_i for one cycle
 353         yield dut.oper_i.insn_type.eq(op)
 354         if hasattr(dut.oper_i, "invert_in"):
 355             yield dut.oper_i.invert_in.eq(inv_a)
 356         if hasattr(dut.oper_i, "imm_data"):
 357             yield dut.oper_i.imm_data.data.eq(imm)
 358             yield dut.oper_i.imm_data.ok.eq(imm_ok)
 359         if hasattr(dut.oper_i, "zero_a"):
 360             yield dut.oper_i.zero_a.eq(zero_a)
 361         if hasattr(dut, "rdmaskn"):
 362             rdmaskn_bits = 0
 363             for i in range(len(rdmaskn)):
 364                 rdmaskn_bits |= rdmaskn[i] << i
 365             yield dut.rdmaskn.eq(rdmaskn_bits)
 366         yield dut.issue_i.eq(1)
 367         yield
 368         yield dut.issue_i.eq(0)
 369         # deactivate decoder inputs along with issue_i, so we can be sure they
 370         # were latched at the correct cycle
 371         # note: rdmaskn is not latched, and must be held as long as
 372         # busy_o is active
 373         # See: https://bugs.libre-soc.org/show_bug.cgi?id=336#c44
 374         yield self.dut.oper_i.insn_type.eq(0)
 375         if hasattr(dut.oper_i, "invert_in"):
 376             yield self.dut.oper_i.invert_in.eq(0)
 377         if hasattr(dut.oper_i, "imm_data"):
 378             yield self.dut.oper_i.imm_data.data.eq(0)
 379             yield self.dut.oper_i.imm_data.ok.eq(0)
 380         if hasattr(dut.oper_i, "zero_a"):
 381             yield self.dut.oper_i.zero_a.eq(0)
 382         # wait for busy to be negated
 383         yield Settle()
 384         while (yield dut.busy_o):
 385             yield
 386             yield Settle()
 387         # now, deactivate rdmaskn
 388         if hasattr(dut, "rdmaskn"):
 389             yield dut.rdmaskn.eq(0)
 390         # update the operation count
 391         self.op_count = (self.op_count + 1) & 255
 392         # On zero_a, imm_ok and rdmaskn executions, the producer counters will
 393         # fall behind. But, by summing the following counts, the invariant is
 394         # preserved.
 395         if zero_a and not rdmaskn[0]:
 396             self.zero_a_count += 1
 397         if imm_ok and not rdmaskn[1]:
 398             self.imm_ok_count += 1
 399         for i in range(len(rdmaskn)):
 400             if rdmaskn[i]:
 401                 self.rdmaskn_count[i] += 1
 402         for i in range(len(wrmask)):
 403             if wrmask[i]:
 404                 self.wrmask_count[i] += 1
 405         # check that producers and consumers have the same count
 406         # this assures that no data was left unused or was lost
 407         # first, check special cases (zero_a and imm_ok)
 408         port_a_cnt = \
 409             (yield producers[0].count) \
 410             + self.zero_a_count \
 411             + self.rdmaskn_count[0]
 412         port_b_cnt = \
 413             (yield producers[1].count) \
 414             + self.imm_ok_count \
 415             + self.rdmaskn_count[1]
 416         assert port_a_cnt == self.op_count
 417         assert port_b_cnt == self.op_count
 418         # then, check the rest (if any)
 419         for i in range(2, len(producers)):
 420             port_cnt = (yield producers[i].count) + self.rdmaskn_count[i]
 421             assert port_cnt == self.op_count
 422         # check write counter
 423         for i in range(len(consumers)):
 424             port_cnt = (yield consumers[i].count) + self.wrmask_count[i]
 425             assert port_cnt == self.op_count
 426
 427
 428 def scoreboard_sim(op):
 429     # zero (no) input operands test
 430     # 0 + 8 = 8
 431     yield from op.issue([5, 2], MicrOp.OP_ADD, [8],
 432                         zero_a=1, imm=8, imm_ok=1,
 433                         src_delays=[0, 2], dest_delays=[0])
 434     # 5 + 8 = 13
 435     yield from op.issue([5, 2], MicrOp.OP_ADD, [13],
 436                         inv_a=0, imm=8, imm_ok=1,
 437                         src_delays=[2, 0], dest_delays=[2])
 438     # 5 + 2 = 7
 439     yield from op.issue([5, 2], MicrOp.OP_ADD, [7],
 440                         src_delays=[1, 1], dest_delays=[1])
 441     # (-6) + 2 = (-4)
 442     yield from op.issue([5, 2], MicrOp.OP_ADD, [65532],
 443                         inv_a=1,
 444                         src_delays=[1, 2], dest_delays=[0])
 445     # 0 + 2 = 2
 446     yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
 447                         zero_a=1,
 448                         src_delays=[2, 0], dest_delays=[1])
 449
 450     # test combinatorial zero-delay operation
 451     # In the test ALU, any operation other than ADD, MUL, EXTS or SHR
 452     # is zero-delay, and do a subtraction.
 453     # 5 - 2 = 3
 454     yield from op.issue([5, 2], MicrOp.OP_CMP, [3],
 455                         src_delays=[0, 1], dest_delays=[2])
 456     # test all combinations of masked input ports
 457     # sign_extend(0x80) = 0xFF80
 458     yield from op.issue([0x80, 2], MicrOp.OP_EXTS, [0xFF80],
 459                         rdmaskn=[0, 1],
 460                         src_delays=[2, 1], dest_delays=[0])
 461     # sign_extend(0x80) = 0xFF80
 462     yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80],
 463                         rdmaskn=[1, 0],
 464                         src_delays=[1, 2], dest_delays=[1])
 465     # 0 (masked) + 0 (masked) = 0
 466     yield from op.issue([5, 2], MicrOp.OP_ADD, [0],
 467                         rdmaskn=[1, 1],
 468                         src_delays=[1, 2], dest_delays=[1])
 469     # note: the current test ALU down not have any masked write operations
 470
 471
 472 def test_compunit_fsm():
 473     style = {
 474         'in': {'color': 'orange'},
 475         'out': {'color': 'yellow'},
 476     }
 477     traces = [
 478         'clk',
 479         ('operation port', {'color': 'red'}, [
 480             'cu_issue_i', 'cu_busy_o',
 481             {'comment': 'operation'},
 482             'oper_i_None__sdir']),
 483         ('operand 1 port', 'in', [
 484             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 485             ('cu_rd__go_i[1:0]', {'bit': 1}),
 486             'src1_i[7:0]']),
 487         ('operand 2 port', 'in', [
 488             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 489             ('cu_rd__go_i[1:0]', {'bit': 0}),
 490             'src2_i[7:0]']),
 491         ('result port', 'out', [
 492             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 493         ('alu', {'submodule': 'alu'}, [
 494             ('prev port', 'in', [
 495                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 496                 ({'submodule': 'p'},
 497                     ['p_valid_i', 'p_ready_o'])]),
 498             ('next port', 'out', [
 499                 'n_data_o[7:0]',
 500                 ({'submodule': 'n'},
 501                     ['n_valid_o', 'n_ready_i'])])]),
 502         ('debug', {'module': 'top'},
 503             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 504
 505     write_gtkw(
 506         "test_compunit_fsm1.gtkw",
 507         "test_compunit_fsm1.vcd",
 508         traces, style,
 509         module='top.cu'
 510     )
 511     m = Module()
 512     alu = Shifter(8)
 513     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 514     m.submodules.cu = dut
 515
 516     vl = rtlil.convert(dut, ports=dut.ports())
 517     with open("test_compunit_fsm1.il", "w") as f:
 518         f.write(vl)
 519
 520     sim = Simulator(m)
 521     sim.add_clock(1e-6)
 522
 523     # create one operand producer for each input port
 524     prod_a = OperandProducer(sim, dut, 0)
 525     prod_b = OperandProducer(sim, dut, 1)
 526     # create an result consumer for the output port
 527     cons = ResultConsumer(sim, dut, 0)
 528     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 529                                                  [prod_a, prod_b],
 530                                                  [cons])))
 531     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 532                                traces=[prod_a.count,
 533                                        prod_b.count,
 534                                        cons.count])
 535     with sim_writer:
 536         sim.run()
 537
 538
 539 def test_compunit():
 540
 541     m = Module()
 542     alu = ALU(16)
 543     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 544     m.submodules.cu = dut
 545
 546     vl = rtlil.convert(dut, ports=dut.ports())
 547     with open("test_compunit1.il", "w") as f:
 548         f.write(vl)
 549
 550     sim = Simulator(m)
 551     sim.add_clock(1e-6)
 552
 553     # create an operation issuer
 554     op = OpSim(dut, sim)
 555     sim.add_sync_process(wrap(scoreboard_sim(op)))
 556     sim_writer = sim.write_vcd('test_compunit1.vcd')
 557     with sim_writer:
 558         sim.run()
 559
 560
 561 def test_compunit_regspec2_fsm():
 562
 563     inspec = [('INT', 'data', '0:15'),
 564               ('INT', 'shift', '0:15')]
 565     outspec = [('INT', 'data', '0:15')]
 566
 567     regspec = (inspec, outspec)
 568
 569     m = Module()
 570     alu = Shifter(8)
 571     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 572     m.submodules.cu = dut
 573
 574     sim = Simulator(m)
 575     sim.add_clock(1e-6)
 576
 577     # create one operand producer for each input port
 578     prod_a = OperandProducer(sim, dut, 0)
 579     prod_b = OperandProducer(sim, dut, 1)
 580     # create an result consumer for the output port
 581     cons = ResultConsumer(sim, dut, 0)
 582     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 583                                                  [prod_a, prod_b],
 584                                                  [cons])))
 585     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 586                                traces=[prod_a.count,
 587                                        prod_b.count,
 588                                        cons.count])
 589     with sim_writer:
 590         sim.run()
 591
 592
 593 def test_compunit_regspec3():
 594
 595     style = {
 596         'in': {'color': 'orange'},
 597         'out': {'color': 'yellow'},
 598     }
 599     traces = [
 600         'clk',
 601         ('operation port', {'color': 'red'}, [
 602             'cu_issue_i', 'cu_busy_o',
 603             {'comment': 'operation'},
 604             ('oper_i_None__insn_type'
 605              + ('' if is_engine_pysim() else '[6:0]'),
 606              {'display': 'insn_type'})]),
 607         ('operand 1 port', 'in', [
 608             ('cu_rdmaskn_i[2:0]', {'bit': 2}),
 609             ('cu_rd__rel_o[2:0]', {'bit': 2}),
 610             ('cu_rd__go_i[2:0]', {'bit': 2}),
 611             'src1_i[15:0]']),
 612         ('operand 2 port', 'in', [
 613             ('cu_rdmaskn_i[2:0]', {'bit': 1}),
 614             ('cu_rd__rel_o[2:0]', {'bit': 1}),
 615             ('cu_rd__go_i[2:0]', {'bit': 1}),
 616             'src2_i[15:0]']),
 617         ('operand 3 port', 'in', [
 618             ('cu_rdmaskn_i[2:0]', {'bit': 0}),
 619             ('cu_rd__rel_o[2:0]', {'bit': 0}),
 620             ('cu_rd__go_i[2:0]', {'bit': 0}),
 621             'src1_i[15:0]']),
 622         ('result port', 'out', [
 623             'cu_wrmask_o', 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 624         ('alu', {'submodule': 'alu'}, [
 625             ('prev port', 'in', [
 626                 'oper_i_None__insn_type', 'i1[15:0]',
 627                 'valid_i', 'ready_o']),
 628             ('next port', 'out', [
 629                 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
 630
 631     write_gtkw("test_compunit_regspec3.gtkw",
 632                "test_compunit_regspec3.vcd",
 633                traces, style,
 634                clk_period=1e-6,
 635                module='top.cu')
 636
 637     inspec = [('INT', 'a', '0:15'),
 638               ('INT', 'b', '0:15'),
 639               ('INT', 'c', '0:15')]
 640     outspec = [('INT', 'o', '0:15')]
 641
 642     regspec = (inspec, outspec)
 643
 644     m = Module()
 645     alu = DummyALU(16)
 646     dut = MultiCompUnit(regspec, alu, CompCROpSubset)
 647     m.submodules.cu = dut
 648
 649     sim = Simulator(m)
 650     sim.add_clock(1e-6)
 651
 652     # create an operation issuer
 653     op = OpSim(dut, sim)
 654     sim.add_sync_process(wrap(scoreboard_sim_dummy(op)))
 655     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 656     with sim_writer:
 657         sim.run()
 658
 659
 660 def test_compunit_regspec1():
 661
 662     style = {
 663         'in': {'color': 'orange'},
 664         'out': {'color': 'yellow'},
 665     }
 666     traces = [
 667         'clk',
 668         ('operation port', {'color': 'red'}, [
 669             'cu_issue_i', 'cu_busy_o',
 670             {'comment': 'operation'},
 671             ('oper_i_None__insn_type'
 672              + ('' if is_engine_pysim() else '[6:0]'),
 673              {'display': 'insn_type'}),
 674             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 675             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 676             ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
 677             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
 678         ('operand 1 port', 'in', [
 679             ('cu_rdmaskn_i[1:0]', {'bit': 1}),
 680             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 681             ('cu_rd__go_i[1:0]', {'bit': 1}),
 682             'src1_i[15:0]']),
 683         ('operand 2 port', 'in', [
 684             ('cu_rdmaskn_i[1:0]', {'bit': 0}),
 685             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 686             ('cu_rd__go_i[1:0]', {'bit': 0}),
 687             'src2_i[15:0]']),
 688         ('result port', 'out', [
 689             'cu_wrmask_o', 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 690         ('alu', {'submodule': 'alu'}, [
 691             ('prev port', 'in', [
 692                 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
 693                 'valid_i', 'ready_o']),
 694             ('next port', 'out', [
 695                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
 696         ('debug', {'module': 'top'},
 697             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 698
 699     write_gtkw("test_compunit_regspec1.gtkw",
 700                "test_compunit_regspec1.vcd",
 701                traces, style,
 702                clk_period=1e-6,
 703                module='top.cu')
 704
 705     inspec = [('INT', 'a', '0:15'),
 706               ('INT', 'b', '0:15')]
 707     outspec = [('INT', 'o', '0:15')]
 708
 709     regspec = (inspec, outspec)
 710
 711     m = Module()
 712     alu = ALU(16)
 713     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 714     m.submodules.cu = dut
 715
 716     vl = rtlil.convert(dut, ports=dut.ports())
 717     with open("test_compunit_regspec1.il", "w") as f:
 718         f.write(vl)
 719
 720     sim = Simulator(m)
 721     sim.add_clock(1e-6)
 722
 723     # create an operation issuer
 724     op = OpSim(dut, sim)
 725     sim.add_sync_process(wrap(scoreboard_sim(op)))
 726     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd',
 727                                traces=[op.producers[0].count,
 728                                        op.producers[1].count,
 729                                        op.consumers[0].count])
 730     with sim_writer:
 731         sim.run()
 732
 733
 734 if __name__ == '__main__':
 735     test_compunit()
 736     test_compunit_fsm()
 737     test_compunit_regspec1()
 738     test_compunit_regspec2_fsm()
 739     test_compunit_regspec3()