src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.experiment.alu_hier import ALU, DummyALU
  16 from soc.experiment.compalu_multi import MultiCompUnit
  17 from soc.decoder.power_enums import MicrOp
  18 from nmutil.gtkw import write_gtkw
  19 from nmigen import Module, Signal
  20 from nmigen.cli import rtlil
  21
  22 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  23 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  24 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  25                                         Passive)
  26
  27
  28 def wrap(process):
  29     def wrapper():
  30         yield from process
  31     return wrapper
  32
  33
  34 class OperandProducer:
  35     """
  36     Produces an operand when requested by the Computation Unit
  37     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  38
  39     Attaches itself to the `dut` operand indexed by `op_index`.
  40
  41     Has a programmable delay between the assertion of `rel_o` and the
  42     `go_i` pulse.
  43
  44     Data is presented only during the cycle in which `go_i` is active.
  45
  46     It adds itself as a passive process to the simulation (`sim` parameter).
  47     Since it is passive, it will not hang the simulation, and does not need a
  48     flag to terminate itself.
  49     """
  50     def __init__(self, sim, dut, op_index):
  51         self.count = Signal(8, name=f"src{op_index + 1}_count")
  52         """ transaction counter"""
  53         # data and handshake signals from the DUT
  54         self.port = dut.src_i[op_index]
  55         self.go_i = dut.rd.go_i[op_index]
  56         self.rel_o = dut.rd.rel_o[op_index]
  57         # transaction parameters, passed via signals
  58         self.delay = Signal(8)
  59         self.data = Signal.like(self.port)
  60         # add ourselves to the simulation process list
  61         sim.add_sync_process(self._process)
  62
  63     def _process(self):
  64         yield Passive()
  65         while True:
  66             # Settle() is needed to give a quick response to
  67             # the zero delay case
  68             yield Settle()
  69             # wait for rel_o to become active
  70             while not (yield self.rel_o):
  71                 yield
  72                 yield Settle()
  73             # read the transaction parameters
  74             delay = (yield self.delay)
  75             data = (yield self.data)
  76             # wait for `delay` cycles
  77             for _ in range(delay):
  78                 yield
  79             # activate go_i and present data, for one cycle
  80             yield self.go_i.eq(1)
  81             yield self.port.eq(data)
  82             yield self.count.eq(self.count + 1)
  83             yield
  84             yield self.go_i.eq(0)
  85             yield self.port.eq(0)
  86
  87     def send(self, data, delay):
  88         """
  89         Schedules the module to send some `data`, counting `delay` cycles after
  90         `rel_i` becomes active.
  91
  92         To be called from the main test-bench process,
  93         it returns in the same cycle.
  94
  95         Communication with the worker process is done by means of
  96         combinatorial simulation-only signals.
  97
  98         """
  99         yield self.data.eq(data)
 100         yield self.delay.eq(delay)
 101
 102
 103 class ResultConsumer:
 104     """
 105     Consumes a result when requested by the Computation Unit
 106     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 107
 108     Attaches itself to the `dut` result indexed by `op_index`.
 109
 110     Has a programmable delay between the assertion of `rel_o` and the
 111     `go_i` pulse.
 112
 113     Data is retrieved only during the cycle in which `go_i` is active.
 114
 115     It adds itself as a passive process to the simulation (`sim` parameter).
 116     Since it is passive, it will not hang the simulation, and does not need a
 117     flag to terminate itself.
 118     """
 119     def __init__(self, sim, dut, op_index):
 120         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 121         """ transaction counter"""
 122         # data and handshake signals from the DUT
 123         self.port = dut.dest[op_index]
 124         self.go_i = dut.wr.go_i[op_index]
 125         self.rel_o = dut.wr.rel_o[op_index]
 126         # transaction parameters, passed via signals
 127         self.delay = Signal(8)
 128         self.expected = Signal.like(self.port)
 129         # add ourselves to the simulation process list
 130         sim.add_sync_process(self._process)
 131
 132     def _process(self):
 133         yield Passive()
 134         while True:
 135             # Settle() is needed to give a quick response to
 136             # the zero delay case
 137             yield Settle()
 138             # wait for rel_o to become active
 139             while not (yield self.rel_o):
 140                 yield
 141                 yield Settle()
 142             # read the transaction parameters
 143             delay = (yield self.delay)
 144             expected = (yield self.expected)
 145             # wait for `delay` cycles
 146             for _ in range(delay):
 147                 yield
 148             # activate go_i for one cycle
 149             yield self.go_i.eq(1)
 150             yield self.count.eq(self.count + 1)
 151             yield
 152             # check received data against the expected value
 153             result = (yield self.port)
 154             assert result == expected,\
 155                 f"expected {expected}, received {result}"
 156             yield self.go_i.eq(0)
 157             yield self.port.eq(0)
 158
 159     def receive(self, expected, delay):
 160         """
 161         Schedules the module to receive some result,
 162         counting `delay` cycles after `rel_i` becomes active.
 163         As 'go_i' goes active, check the result with `expected`.
 164
 165         To be called from the main test-bench process,
 166         it returns in the same cycle.
 167
 168         Communication with the worker process is done by means of
 169         combinatorial simulation-only signals.
 170         """
 171         yield self.expected.eq(expected)
 172         yield self.delay.eq(delay)
 173
 174
 175 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 176     yield dut.issue_i.eq(0)
 177     yield
 178     yield dut.src_i[0].eq(a)
 179     yield dut.src_i[1].eq(b)
 180     yield dut.oper_i.insn_type.eq(op)
 181     yield dut.oper_i.invert_in.eq(inv_a)
 182     yield dut.oper_i.imm_data.data.eq(imm)
 183     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 184     yield dut.oper_i.zero_a.eq(zero_a)
 185     yield dut.issue_i.eq(1)
 186     yield
 187     yield dut.issue_i.eq(0)
 188     yield
 189     if not imm_ok or not zero_a:
 190         yield dut.rd.go_i.eq(0b11)
 191         while True:
 192             yield
 193             rd_rel_o = yield dut.rd.rel_o
 194             print("rd_rel", rd_rel_o)
 195             if rd_rel_o:
 196                 break
 197         yield dut.rd.go_i.eq(0)
 198     else:
 199         print("no go rd")
 200
 201     if len(dut.src_i) == 3:
 202         yield dut.rd.go_i.eq(0b100)
 203         while True:
 204             yield
 205             rd_rel_o = yield dut.rd.rel_o
 206             print("rd_rel", rd_rel_o)
 207             if rd_rel_o:
 208                 break
 209         yield dut.rd.go_i.eq(0)
 210     else:
 211         print("no 3rd rd")
 212
 213     req_rel_o = yield dut.wr.rel_o
 214     result = yield dut.data_o
 215     print("req_rel", req_rel_o, result)
 216     while True:
 217         req_rel_o = yield dut.wr.rel_o
 218         result = yield dut.data_o
 219         print("req_rel", req_rel_o, result)
 220         if req_rel_o:
 221             break
 222         yield
 223     yield dut.wr.go_i[0].eq(1)
 224     yield Settle()
 225     result = yield dut.data_o
 226     yield
 227     print("result", result)
 228     yield dut.wr.go_i[0].eq(0)
 229     yield
 230     return result
 231
 232
 233 def scoreboard_sim_fsm(dut, producers, consumers):
 234
 235     # stores the operation count
 236     op_count = 0
 237
 238     def op_sim_fsm(a, b, direction, expected, delays):
 239         print("op_sim_fsm", a, b, direction, expected)
 240         yield dut.issue_i.eq(0)
 241         yield
 242         # forward data and delays to the producers and consumers
 243         yield from producers[0].send(a, delays[0])
 244         yield from producers[1].send(b, delays[1])
 245         yield from consumers[0].receive(expected, delays[2])
 246         # submit operation, and assert issue_i for one cycle
 247         yield dut.oper_i.sdir.eq(direction)
 248         yield dut.issue_i.eq(1)
 249         yield
 250         yield dut.issue_i.eq(0)
 251         # wait for busy to be negated
 252         yield Settle()
 253         while (yield dut.busy_o):
 254             yield
 255             yield Settle()
 256         # update the operation count
 257         nonlocal op_count
 258         op_count = (op_count + 1) & 255
 259         # check that producers and consumers have the same count
 260         # this assures that no data was left unused or was lost
 261         assert (yield producers[0].count) == op_count
 262         assert (yield producers[1].count) == op_count
 263         assert (yield consumers[0].count) == op_count
 264
 265     # 13 >> 2 = 3
 266     # operand 1 arrives immediately
 267     # operand 2 arrives after operand 1
 268     # write data is accepted immediately
 269     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 270     # 3 << 4 = 48
 271     # operand 2 arrives immediately
 272     # operand 1 arrives after operand 2
 273     # write data is accepted after some delay
 274     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 275     # 21 << 0 = 21
 276     # operands 1 and 2 arrive at the same time
 277     # write data is accepted after some delay
 278     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 279
 280
 281 def scoreboard_sim_dummy(dut):
 282     result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
 283                                imm=8, imm_ok=1)
 284     assert result == 5, result
 285
 286     result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
 287                                imm=8, imm_ok=1)
 288     assert result == 9, result
 289
 290
 291 def scoreboard_sim(dut):
 292     # zero (no) input operands test
 293     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
 294                                imm=8, imm_ok=1)
 295     assert result == 8
 296
 297     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
 298                                imm=8, imm_ok=1)
 299     assert result == 13
 300
 301     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
 302     assert result == 7
 303
 304     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
 305     assert result == 65532
 306
 307     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1)
 308     assert result == 2
 309
 310     # test combinatorial zero-delay operation
 311     # In the test ALU, any operation other than ADD, MUL or SHR
 312     # is zero-delay, and do a subtraction.
 313     result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP)
 314     assert result == 3
 315
 316
 317 def test_compunit_fsm():
 318     top = "top.cu" if is_engine_pysim() else "cu"
 319     style = {
 320         'in': {'color': 'orange'},
 321         'out': {'color': 'yellow'},
 322     }
 323     traces = [
 324         'clk',
 325         ('operation port', {'color': 'red'}, [
 326             'cu_issue_i', 'cu_busy_o',
 327             {'comment': 'operation'},
 328             'oper_i_None__sdir']),
 329         ('operand 1 port', 'in', [
 330             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 331             ('cu_rd__go_i[1:0]', {'bit': 1}),
 332             'src1_i[7:0]']),
 333         ('operand 2 port', 'in', [
 334             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 335             ('cu_rd__go_i[1:0]', {'bit': 0}),
 336             'src2_i[7:0]']),
 337         ('result port', 'out', [
 338             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 339         ('alu', {'module': top+'.alu'}, [
 340             ('prev port', 'in', [
 341                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 342                 'p_valid_i', 'p_ready_o']),
 343             ('next port', 'out', [
 344                 'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']),
 345         ]),
 346         ('debug', {'module': 'top'},
 347          ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])
 348
 349     ]
 350     write_gtkw(
 351         "test_compunit_fsm1.gtkw",
 352         "test_compunit_fsm1.vcd",
 353         traces, style,
 354         module=top
 355     )
 356     m = Module()
 357     alu = Shifter(8)
 358     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 359     m.submodules.cu = dut
 360
 361     vl = rtlil.convert(dut, ports=dut.ports())
 362     with open("test_compunit_fsm1.il", "w") as f:
 363         f.write(vl)
 364
 365     sim = Simulator(m)
 366     sim.add_clock(1e-6)
 367
 368     # create one operand producer for each input port
 369     prod_a = OperandProducer(sim, dut, 0)
 370     prod_b = OperandProducer(sim, dut, 1)
 371     # create an result consumer for the output port
 372     cons = ResultConsumer(sim, dut, 0)
 373     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 374                                                  [prod_a, prod_b],
 375                                                  [cons])))
 376     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 377                                traces=[prod_a.count,
 378                                        prod_b.count,
 379                                        cons.count])
 380     with sim_writer:
 381         sim.run()
 382
 383
 384 def test_compunit():
 385
 386     m = Module()
 387     alu = ALU(16)
 388     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 389     m.submodules.cu = dut
 390
 391     vl = rtlil.convert(dut, ports=dut.ports())
 392     with open("test_compunit1.il", "w") as f:
 393         f.write(vl)
 394
 395     sim = Simulator(m)
 396     sim.add_clock(1e-6)
 397
 398     sim.add_sync_process(wrap(scoreboard_sim(dut)))
 399     sim_writer = sim.write_vcd('test_compunit1.vcd')
 400     with sim_writer:
 401         sim.run()
 402
 403
 404 class CompUnitParallelTest:
 405     def __init__(self, dut):
 406         self.dut = dut
 407
 408         # Operation cycle should not take longer than this:
 409         self.MAX_BUSY_WAIT = 50
 410
 411         # Minimum duration in which issue_i will be kept inactive,
 412         # during which busy_o must remain low.
 413         self.MIN_BUSY_LOW = 5
 414
 415         # Number of cycles to stall until the assertion of go.
 416         # One value, for each port. Can be zero, for no delay.
 417         self.RD_GO_DELAY = [0, 3]
 418
 419         # store common data for the input operation of the processes
 420         # input operation:
 421         self.op = 0
 422         self.inv_a = self.zero_a = 0
 423         self.imm = self.imm_ok = 0
 424         self.imm_control = (0, 0)
 425         self.rdmaskn = (0, 0)
 426         # input data:
 427         self.operands = (0, 0)
 428
 429         # Indicates completion of the sub-processes
 430         self.rd_complete = [False, False]
 431
 432     def driver(self):
 433         print("Begin parallel test.")
 434         yield from self.operation(5, 2, MicrOp.OP_ADD)
 435
 436     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 437                   rdmaskn=(0, 0)):
 438         # store data for the operation
 439         self.operands = (a, b)
 440         self.op = op
 441         self.inv_a = inv_a
 442         self.imm = imm
 443         self.imm_ok = imm_ok
 444         self.zero_a = zero_a
 445         self.imm_control = (zero_a, imm_ok)
 446         self.rdmaskn = rdmaskn
 447
 448         # Initialize completion flags
 449         self.rd_complete = [False, False]
 450
 451         # trigger operation cycle
 452         yield from self.issue()
 453
 454         # check that the sub-processes completed, before the busy_o cycle ended
 455         for completion in self.rd_complete:
 456             assert completion
 457
 458     def issue(self):
 459         # issue_i starts inactive
 460         yield self.dut.issue_i.eq(0)
 461
 462         for n in range(self.MIN_BUSY_LOW):
 463             yield
 464             # busy_o must remain inactive. It cannot rise on its own.
 465             busy_o = yield self.dut.busy_o
 466             assert not busy_o
 467
 468         # activate issue_i to begin the operation cycle
 469         yield self.dut.issue_i.eq(1)
 470
 471         # at the same time, present the operation
 472         yield self.dut.oper_i.insn_type.eq(self.op)
 473         yield self.dut.oper_i.invert_in.eq(self.inv_a)
 474         yield self.dut.oper_i.imm_data.data.eq(self.imm)
 475         yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok)
 476         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 477         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 478         yield self.dut.rdmaskn.eq(rdmaskn)
 479
 480         # give one cycle for the CompUnit to latch the data
 481         yield
 482
 483         # busy_o must keep being low in this cycle, because issue_i was
 484         # low on the previous cycle.
 485         # It cannot rise on its own.
 486         # Also, busy_o and issue_i must never be active at the same time, ever.
 487         busy_o = yield self.dut.busy_o
 488         assert not busy_o
 489
 490         # Lower issue_i
 491         yield self.dut.issue_i.eq(0)
 492
 493         # deactivate inputs along with issue_i, so we can be sure the data
 494         # was latched at the correct cycle
 495         # note: rdmaskn must be held, while busy_o is active
 496         # TODO: deactivate rdmaskn when the busy_o cycle ends
 497         yield self.dut.oper_i.insn_type.eq(0)
 498         yield self.dut.oper_i.invert_in.eq(0)
 499         yield self.dut.oper_i.imm_data.data.eq(0)
 500         yield self.dut.oper_i.imm_data.ok.eq(0)
 501         yield self.dut.oper_i.zero_a.eq(0)
 502         yield
 503
 504         # wait for busy_o to lower
 505         # timeout after self.MAX_BUSY_WAIT cycles
 506         for n in range(self.MAX_BUSY_WAIT):
 507             # sample busy_o in the current cycle
 508             busy_o = yield self.dut.busy_o
 509             if not busy_o:
 510                 # operation cycle ends when busy_o becomes inactive
 511                 break
 512             yield
 513
 514         # if busy_o is still active, a timeout has occurred
 515         # TODO: Uncomment this, once the test is complete:
 516         # assert not busy_o
 517
 518         if busy_o:
 519             print("If you are reading this, "
 520                   "it's because the above test failed, as expected,\n"
 521                   "with a timeout. It must pass, once the test is complete.")
 522             return
 523
 524         print("If you are reading this, "
 525               "it's because the above test unexpectedly passed.")
 526
 527     def rd(self, rd_idx):
 528         # wait for issue_i to rise
 529         while True:
 530             issue_i = yield self.dut.issue_i
 531             if issue_i:
 532                 break
 533             # issue_i has not risen yet, so rd must keep low
 534             rel = yield self.dut.rd.rel_o[rd_idx]
 535             assert not rel
 536             yield
 537
 538         # we do not want rd to rise on an immediate operand
 539         # if it is immediate, exit the process
 540         # likewise, if the read mask is active
 541         # TODO: don't exit the process, monitor rd instead to ensure it
 542         #       doesn't rise on its own
 543         if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
 544             self.rd_complete[rd_idx] = True
 545             return
 546
 547         # issue_i has risen. rel must rise on the next cycle
 548         rel = yield self.dut.rd.rel_o[rd_idx]
 549         assert not rel
 550
 551         # stall for additional cycles. Check that rel doesn't fall on its own
 552         for n in range(self.RD_GO_DELAY[rd_idx]):
 553             yield
 554             rel = yield self.dut.rd.rel_o[rd_idx]
 555             assert rel
 556
 557         # Before asserting "go", make sure "rel" has risen.
 558         # The use of Settle allows "go" to be set combinatorially,
 559         # rising on the same cycle as "rel".
 560         yield Settle()
 561         rel = yield self.dut.rd.rel_o[rd_idx]
 562         assert rel
 563
 564         # assert go for one cycle, passing along the operand value
 565         yield self.dut.rd.go_i[rd_idx].eq(1)
 566         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
 567         # check that the operand was sent to the alu
 568         # TODO: Properly check the alu protocol
 569         yield Settle()
 570         alu_input = yield self.dut.get_in(rd_idx)
 571         assert alu_input == self.operands[rd_idx]
 572         yield
 573
 574         # rel must keep high, since go was inactive in the last cycle
 575         rel = yield self.dut.rd.rel_o[rd_idx]
 576         assert rel
 577
 578         # finish the go one-clock pulse
 579         yield self.dut.rd.go_i[rd_idx].eq(0)
 580         yield self.dut.src_i[rd_idx].eq(0)
 581         yield
 582
 583         # rel must have gone low in response to go being high
 584         # on the previous cycle
 585         rel = yield self.dut.rd.rel_o[rd_idx]
 586         assert not rel
 587
 588         self.rd_complete[rd_idx] = True
 589
 590         # TODO: check that rel doesn't rise again until the end of the
 591         #       busy_o cycle
 592
 593     def wr(self, wr_idx):
 594         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 595         yield
 596         # TODO: also when dut.wr.go is set, check the output against the
 597         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 598
 599     def run_simulation(self, vcd_name):
 600         m = Module()
 601         m.submodules.cu = self.dut
 602         sim = Simulator(m)
 603         sim.add_clock(1e-6)
 604
 605         sim.add_sync_process(wrap(self.driver()))
 606         sim.add_sync_process(wrap(self.rd(0)))
 607         sim.add_sync_process(wrap(self.rd(1)))
 608         sim.add_sync_process(wrap(self.wr(0)))
 609         sim_writer = sim.write_vcd(vcd_name)
 610         with sim_writer:
 611             sim.run()
 612
 613
 614 def test_compunit_regspec2_fsm():
 615
 616     inspec = [('INT', 'data', '0:15'),
 617               ('INT', 'shift', '0:15'),
 618               ]
 619     outspec = [('INT', 'data', '0:15'),
 620                ]
 621
 622     regspec = (inspec, outspec)
 623
 624     m = Module()
 625     alu = Shifter(8)
 626     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 627     m.submodules.cu = dut
 628
 629     sim = Simulator(m)
 630     sim.add_clock(1e-6)
 631
 632     # create one operand producer for each input port
 633     prod_a = OperandProducer(sim, dut, 0)
 634     prod_b = OperandProducer(sim, dut, 1)
 635     # create an result consumer for the output port
 636     cons = ResultConsumer(sim, dut, 0)
 637     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 638                                                  [prod_a, prod_b],
 639                                                  [cons])))
 640     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 641                                traces=[prod_a.count,
 642                                        prod_b.count,
 643                                        cons.count])
 644     with sim_writer:
 645         sim.run()
 646
 647
 648 def test_compunit_regspec3():
 649
 650     inspec = [('INT', 'a', '0:15'),
 651               ('INT', 'b', '0:15'),
 652               ('INT', 'c', '0:15')]
 653     outspec = [('INT', 'o', '0:15'),
 654                ]
 655
 656     regspec = (inspec, outspec)
 657
 658     m = Module()
 659     alu = DummyALU(16)
 660     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 661     m.submodules.cu = dut
 662
 663     sim = Simulator(m)
 664     sim.add_clock(1e-6)
 665
 666     sim.add_sync_process(wrap(scoreboard_sim_dummy(dut)))
 667     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 668     with sim_writer:
 669         sim.run()
 670
 671
 672 def test_compunit_regspec1():
 673
 674     style = {
 675         'in': {'color': 'orange'},
 676         'out': {'color': 'yellow'},
 677     }
 678     traces = [
 679         'clk',
 680         ('operation port', {'color': 'red'}, [
 681             'cu_issue_i', 'cu_busy_o',
 682             {'comment': 'operation'},
 683             ('oper_i_None__insn_type', {'display': 'insn_type'}),
 684             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 685             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 686             ('oper_i_None__imm_data__imm_ok', {'display': 'imm_ok'}),
 687             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
 688         ('operand 1 port', 'in', [
 689             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 690             ('cu_rd__go_i[1:0]', {'bit': 1}),
 691             'src1_i[15:0]']),
 692         ('operand 2 port', 'in', [
 693             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 694             ('cu_rd__go_i[1:0]', {'bit': 0}),
 695             'src2_i[15:0]']),
 696         ('result port', 'out', [
 697             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 698         ('alu', {'module': 'top.cu.alu'}, [
 699             ('prev port', 'in', [
 700                 'op__insn_type', 'op__invert_i', 'a[15:0]', 'b[15:0]',
 701                 'valid_i', 'ready_o']),
 702             ('next port', 'out', [
 703                 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
 704     write_gtkw("test_compunit_regspec1.gtkw",
 705                "test_compunit_regspec1.vcd",
 706                traces, style,
 707                clk_period=1e-6,
 708                module='top.cu')
 709
 710     inspec = [('INT', 'a', '0:15'),
 711               ('INT', 'b', '0:15')]
 712     outspec = [('INT', 'o', '0:15'),
 713                ]
 714
 715     regspec = (inspec, outspec)
 716
 717     m = Module()
 718     alu = ALU(16)
 719     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 720     m.submodules.cu = dut
 721
 722     vl = rtlil.convert(dut, ports=dut.ports())
 723     with open("test_compunit_regspec1.il", "w") as f:
 724         f.write(vl)
 725
 726     sim = Simulator(m)
 727     sim.add_clock(1e-6)
 728
 729     sim.add_sync_process(wrap(scoreboard_sim(dut)))
 730     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd')
 731     with sim_writer:
 732         sim.run()
 733
 734     test = CompUnitParallelTest(dut)
 735     test.run_simulation("test_compunit_parallel.vcd")
 736
 737
 738 if __name__ == '__main__':
 739     test_compunit()
 740     test_compunit_fsm()
 741     test_compunit_regspec1()
 742     test_compunit_regspec2_fsm()
 743     test_compunit_regspec3()