1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from nmigen
.compat
.sim
import run_simulation
, Settle
14 from nmigen
.cli
import verilog
, rtlil
15 from nmigen
import Module
, Signal
, Mux
, Elaboratable
, Repl
, Array
, Cat
, Const
16 from nmigen
.hdl
.rec
import (Record
, DIR_FANIN
, DIR_FANOUT
)
18 from nmutil
.latch
import SRLatch
, latchregister
19 from nmutil
.iocontrol
import RecordObject
21 from soc
.decoder
.power_decoder2
import Data
22 from soc
.decoder
.power_enums
import InternalOp
23 from soc
.fu
.regspec
import RegSpec
, RegSpecALUAPI
25 from soc
.experiment
.compalu_multi
import MultiCompUnit
26 from soc
.experiment
.alu_hier
import ALU
, DummyALU
27 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
30 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
31 yield dut
.issue_i
.eq(0)
33 yield dut
.src_i
[0].eq(a
)
34 yield dut
.src_i
[1].eq(b
)
35 yield dut
.oper_i
.insn_type
.eq(op
)
36 yield dut
.oper_i
.invert_a
.eq(inv_a
)
37 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
38 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
39 yield dut
.oper_i
.zero_a
.eq(zero_a
)
40 yield dut
.issue_i
.eq(1)
42 yield dut
.issue_i
.eq(0)
44 if not imm_ok
or not zero_a
:
45 yield dut
.rd
.go
.eq(0b11)
48 rd_rel_o
= yield dut
.rd
.rel
49 print ("rd_rel", rd_rel_o
)
53 if len(dut
.src_i
) == 3:
54 yield dut
.rd
.go
.eq(0b100)
57 rd_rel_o
= yield dut
.rd
.rel
58 print ("rd_rel", rd_rel_o
)
63 req_rel_o
= yield dut
.wr
.rel
64 result
= yield dut
.data_o
65 print ("req_rel", req_rel_o
, result
)
67 req_rel_o
= yield dut
.wr
.rel
68 result
= yield dut
.data_o
69 print ("req_rel", req_rel_o
, result
)
73 yield dut
.wr
.go
[0].eq(1)
75 result
= yield dut
.data_o
77 print ("result", result
)
78 yield dut
.wr
.go
[0].eq(0)
83 def scoreboard_sim_dummy(dut
):
84 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_NOP
, inv_a
=0,
86 assert result
== 5, result
88 result
= yield from op_sim(dut
, 9, 2, InternalOp
.OP_NOP
, inv_a
=0,
90 assert result
== 9, result
93 def scoreboard_sim(dut
):
94 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=0,
98 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
)
101 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, inv_a
=1)
102 assert result
== 65532
104 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, zero_a
=1,
108 result
= yield from op_sim(dut
, 5, 2, InternalOp
.OP_ADD
, zero_a
=1)
116 dut
= MultiCompUnit(16, alu
, CompALUOpSubset
)
117 m
.submodules
.cu
= dut
119 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
120 with
open("test_compunit1.il", "w") as f
:
123 run_simulation(m
, scoreboard_sim(dut
), vcd_name
='test_compunit1.vcd')
126 class CompUnitParallelTest
:
127 def __init__(self
, dut
):
130 # Operation cycle should not take longer than this:
131 self
.MAX_BUSY_WAIT
= 50
133 # Minimum duration in which issue_i will be kept inactive,
134 # during which busy_o must remain low.
135 self
.MIN_BUSY_LOW
= 5
137 # Number of cycles to stall until the assertion of go.
138 # One value, for each port. Can be zero, for no delay.
139 self
.RD_GO_DELAY
= [0, 3]
141 # store common data for the input operation of the processes
144 self
.inv_a
= self
.zero_a
= 0
145 self
.imm
= self
.imm_ok
= 0
150 print("Begin parallel test.")
151 yield from self
.operation(5, 2, InternalOp
.OP_ADD
, inv_a
=0,
154 def operation(self
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
155 # store data for the operation
164 # trigger operation cycle
165 yield from self
.issue()
168 # issue_i starts inactive
169 yield self
.dut
.issue_i
.eq(0)
171 for n
in range(self
.MIN_BUSY_LOW
):
173 # busy_o must remain inactive. It cannot rise on its own.
174 busy_o
= yield self
.dut
.busy_o
177 # activate issue_i to begin the operation cycle
178 yield self
.dut
.issue_i
.eq(1)
180 # at the same time, present the operation
181 yield self
.dut
.oper_i
.insn_type
.eq(self
.op
)
182 yield self
.dut
.oper_i
.invert_a
.eq(self
.inv_a
)
183 yield self
.dut
.oper_i
.imm_data
.imm
.eq(self
.imm
)
184 yield self
.dut
.oper_i
.imm_data
.imm_ok
.eq(self
.imm_ok
)
185 yield self
.dut
.oper_i
.zero_a
.eq(self
.zero_a
)
187 # give one cycle for the CompUnit to latch the data
190 # busy_o must keep being low in this cycle, because issue_i was
191 # low on the previous cycle.
192 # It cannot rise on its own.
193 # Also, busy_o and issue_i must never be active at the same time, ever.
194 busy_o
= yield self
.dut
.busy_o
198 yield self
.dut
.issue_i
.eq(0)
200 # deactivate inputs along with issue_i, so we can be sure the data
201 # was latched at the correct cycle
202 yield self
.dut
.oper_i
.insn_type
.eq(0)
203 yield self
.dut
.oper_i
.invert_a
.eq(0)
204 yield self
.dut
.oper_i
.imm_data
.imm
.eq(0)
205 yield self
.dut
.oper_i
.imm_data
.imm_ok
.eq(0)
206 yield self
.dut
.oper_i
.zero_a
.eq(0)
209 # wait for busy_o to lower
210 # timeout after self.MAX_BUSY_WAIT cycles
211 for n
in range(self
.MAX_BUSY_WAIT
):
212 # sample busy_o in the current cycle
213 busy_o
= yield self
.dut
.busy_o
215 # operation cycle ends when busy_o becomes inactive
219 # if busy_o is still active, a timeout has occurred
220 # TODO: Uncomment this, once the test is complete:
224 print("If you are reading this, "
225 "it's because the above test failed, as expected,\n"
226 "with a timeout. It must pass, once the test is complete.")
229 print("If you are reading this, "
230 "it's because the above test unexpectedly passed.")
232 def rd(self
, rd_idx
):
233 # wait for issue_i to rise
235 issue_i
= yield self
.dut
.issue_i
238 # issue_i has not risen yet, so rd must keep low
239 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
243 # we do not want rd to rise on an immediate operand
244 # if it is immediate, exit the process
245 # TODO: don't exit the process, monitor rd instead to ensure it
246 # doesn't rise on its own
247 if (self
.zero_a
and rd_idx
== 0) or (self
.imm_ok
and rd_idx
== 1):
250 # issue_i has risen. rel must rise on the next cycle
251 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
254 # stall for additional cycles. Check that rel doesn't fall on its own
255 for n
in range(self
.RD_GO_DELAY
[rd_idx
]):
257 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
260 # Before asserting "go", make sure "rel" has risen.
261 # The use of Settle allows "go" to be set combinatorially,
262 # rising on the same cycle as "rel".
264 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
267 # assert go for one cycle
268 yield self
.dut
.rd
.go
[rd_idx
].eq(1)
271 # rel must keep high, since go was inactive in the last cycle
272 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
275 # finish the go one-clock pulse
276 yield self
.dut
.rd
.go
[rd_idx
].eq(0)
279 # rel must have gone low in response to go being high
280 # on the previous cycle
281 rel
= yield self
.dut
.rd
.rel
[rd_idx
]
284 # TODO: also when dut.rd.go is set, put the expected value into
285 # the src_i. use dut.get_in[rd_idx] to do so
287 def wr(self
, wr_idx
):
288 # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
290 # TODO: also when dut.wr.go is set, check the output against the
291 # self.expected_o and assert. use dut.get_out(wr_idx) to do so.
293 def run_simulation(self
, vcd_name
):
294 run_simulation(self
.dut
, [self
.driver(),
295 self
.rd(0), # one read port (a)
296 self
.rd(1), # one read port (b)
297 self
.wr(0), # one write port (o)
302 def test_compunit_regspec3():
304 inspec
= [('INT', 'a', '0:15'),
305 ('INT', 'b', '0:15'),
306 ('INT', 'c', '0:15')]
307 outspec
= [('INT', 'o', '0:15'),
310 regspec
= (inspec
, outspec
)
314 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
315 m
.submodules
.cu
= dut
317 run_simulation(m
, scoreboard_sim_dummy(dut
),
318 vcd_name
='test_compunit_regspec3.vcd')
321 def test_compunit_regspec1():
323 inspec
= [('INT', 'a', '0:15'),
324 ('INT', 'b', '0:15')]
325 outspec
= [('INT', 'o', '0:15'),
328 regspec
= (inspec
, outspec
)
332 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
333 m
.submodules
.cu
= dut
335 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
336 with
open("test_compunit_regspec1.il", "w") as f
:
339 run_simulation(m
, scoreboard_sim(dut
),
340 vcd_name
='test_compunit_regspec1.vcd')
342 test
= CompUnitParallelTest(dut
)
343 test
.run_simulation("test_compunit_parallel.vcd")
346 if __name__
== '__main__':
348 test_compunit_regspec1()
349 test_compunit_regspec3()