src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 cxxsim = False
  14 if cxxsim:
  15     from nmigen.sim.cxxsim import Simulator, Settle
  16 else:
  17     from nmigen.back.pysim import Simulator, Settle
  18
  19 from nmigen.cli import rtlil
  20 from nmigen import Module
  21
  22 from soc.decoder.power_enums import MicrOp
  23
  24 from soc.experiment.compalu_multi import MultiCompUnit
  25 from soc.experiment.alu_hier import ALU, DummyALU
  26 from soc.fu.alu.alu_input_record import CompALUOpSubset
  27 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  28
  29 def wrap(process):
  30     def wrapper():
  31         yield from process
  32     return wrapper
  33
  34
  35 def op_sim_fsm(dut, a, b, direction):
  36     print ("op_sim_fsm", a, b, direction)
  37     yield dut.issue_i.eq(0)
  38     yield
  39     yield dut.src_i[0].eq(a)
  40     yield dut.src_i[1].eq(b)
  41     yield dut.oper_i.sdir.eq(direction)
  42     yield dut.issue_i.eq(1)
  43     yield
  44     yield dut.issue_i.eq(0)
  45     yield
  46
  47     yield dut.rd.go.eq(0b11)
  48     while True:
  49         yield
  50         rd_rel_o = yield dut.rd.rel
  51         print ("rd_rel", rd_rel_o)
  52         if rd_rel_o:
  53             break
  54     yield dut.rd.go.eq(0)
  55
  56     req_rel_o = yield dut.wr.rel
  57     result = yield dut.data_o
  58     print ("req_rel", req_rel_o, result)
  59     while True:
  60         req_rel_o = yield dut.wr.rel
  61         result = yield dut.data_o
  62         print ("req_rel", req_rel_o, result)
  63         if req_rel_o:
  64             break
  65         yield
  66     yield dut.wr.go[0].eq(1)
  67     yield Settle()
  68     result = yield dut.data_o
  69     yield
  70     print ("result", result)
  71     yield dut.wr.go[0].eq(0)
  72     yield
  73     return result
  74
  75
  76 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
  77     yield dut.issue_i.eq(0)
  78     yield
  79     yield dut.src_i[0].eq(a)
  80     yield dut.src_i[1].eq(b)
  81     yield dut.oper_i.insn_type.eq(op)
  82     yield dut.oper_i.invert_a.eq(inv_a)
  83     yield dut.oper_i.imm_data.imm.eq(imm)
  84     yield dut.oper_i.imm_data.imm_ok.eq(imm_ok)
  85     yield dut.oper_i.zero_a.eq(zero_a)
  86     yield dut.issue_i.eq(1)
  87     yield
  88     yield dut.issue_i.eq(0)
  89     yield
  90     if not imm_ok or not zero_a:
  91         yield dut.rd.go.eq(0b11)
  92         while True:
  93             yield
  94             rd_rel_o = yield dut.rd.rel
  95             print ("rd_rel", rd_rel_o)
  96             if rd_rel_o:
  97                 break
  98         yield dut.rd.go.eq(0)
  99     if len(dut.src_i) == 3:
 100         yield dut.rd.go.eq(0b100)
 101         while True:
 102             yield
 103             rd_rel_o = yield dut.rd.rel
 104             print ("rd_rel", rd_rel_o)
 105             if rd_rel_o:
 106                 break
 107         yield dut.rd.go.eq(0)
 108
 109     req_rel_o = yield dut.wr.rel
 110     result = yield dut.data_o
 111     print ("req_rel", req_rel_o, result)
 112     while True:
 113         req_rel_o = yield dut.wr.rel
 114         result = yield dut.data_o
 115         print ("req_rel", req_rel_o, result)
 116         if req_rel_o:
 117             break
 118         yield
 119     yield dut.wr.go[0].eq(1)
 120     yield Settle()
 121     result = yield dut.data_o
 122     yield
 123     print ("result", result)
 124     yield dut.wr.go[0].eq(0)
 125     yield
 126     return result
 127
 128
 129 def scoreboard_sim_fsm(dut):
 130     result = yield from op_sim_fsm(dut, 13, 2, 1)
 131     assert result == 3, result
 132
 133     result = yield from op_sim_fsm(dut, 3, 4, 0)
 134     assert result == 48, result
 135
 136     result = yield from op_sim_fsm(dut, 21, 0, 0)
 137     assert result == 21, result
 138
 139
 140 def scoreboard_sim_dummy(dut):
 141     result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0,
 142                                     imm=8, imm_ok=1)
 143     assert result == 5, result
 144
 145     result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0,
 146                                     imm=8, imm_ok=1)
 147     assert result == 9, result
 148
 149
 150
 151 def scoreboard_sim(dut):
 152     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0,
 153                                     imm=8, imm_ok=1)
 154     assert result == 13
 155
 156     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD)
 157     assert result == 7
 158
 159     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=1)
 160     assert result == 65532
 161
 162     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1,
 163                                     imm=8, imm_ok=1)
 164     assert result == 8
 165
 166     result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1)
 167     assert result == 2
 168
 169     # test combinatorial zero-delay operation
 170     # In the test ALU, any operation other than ADD, MUL or SHR
 171     # is zero-delay, and do a subtraction.
 172     result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP)
 173     assert result == 3
 174
 175
 176 def test_compunit_fsm():
 177
 178     m = Module()
 179     alu = Shifter(8)
 180     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 181     m.submodules.cu = dut
 182
 183     vl = rtlil.convert(dut, ports=dut.ports())
 184     with open("test_compunit_fsm1.il", "w") as f:
 185         f.write(vl)
 186
 187     sim = Simulator(m)
 188     sim.add_clock(1e-6)
 189
 190     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut)))
 191     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd')
 192     with sim_writer:
 193         sim.run()
 194
 195
 196 def test_compunit():
 197
 198     m = Module()
 199     alu = ALU(16)
 200     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 201     m.submodules.cu = dut
 202
 203     vl = rtlil.convert(dut, ports=dut.ports())
 204     with open("test_compunit1.il", "w") as f:
 205         f.write(vl)
 206
 207     sim = Simulator(m)
 208     sim.add_clock(1e-6)
 209
 210     sim.add_sync_process(wrap(scoreboard_sim(dut)))
 211     sim_writer = sim.write_vcd('test_compunit1.vcd')
 212     with sim_writer:
 213         sim.run()
 214
 215
 216 class CompUnitParallelTest:
 217     def __init__(self, dut):
 218         self.dut = dut
 219
 220         # Operation cycle should not take longer than this:
 221         self.MAX_BUSY_WAIT = 50
 222
 223         # Minimum duration in which issue_i will be kept inactive,
 224         # during which busy_o must remain low.
 225         self.MIN_BUSY_LOW = 5
 226
 227         # Number of cycles to stall until the assertion of go.
 228         # One value, for each port. Can be zero, for no delay.
 229         self.RD_GO_DELAY = [0, 3]
 230
 231         # store common data for the input operation of the processes
 232         # input operation:
 233         self.op = 0
 234         self.inv_a = self.zero_a = 0
 235         self.imm = self.imm_ok = 0
 236         self.imm_control = (0, 0)
 237         self.rdmaskn = (0, 0)
 238         # input data:
 239         self.operands = (0, 0)
 240
 241         # Indicates completion of the sub-processes
 242         self.rd_complete = [False, False]
 243
 244     def driver(self):
 245         print("Begin parallel test.")
 246         yield from self.operation(5, 2, MicrOp.OP_ADD)
 247
 248     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 249                   rdmaskn=(0, 0)):
 250         # store data for the operation
 251         self.operands = (a, b)
 252         self.op = op
 253         self.inv_a = inv_a
 254         self.imm = imm
 255         self.imm_ok = imm_ok
 256         self.zero_a = zero_a
 257         self.imm_control = (zero_a, imm_ok)
 258         self.rdmaskn = rdmaskn
 259
 260         # Initialize completion flags
 261         self.rd_complete = [False, False]
 262
 263         # trigger operation cycle
 264         yield from self.issue()
 265
 266         # check that the sub-processes completed, before the busy_o cycle ended
 267         for completion in self.rd_complete:
 268             assert completion
 269
 270     def issue(self):
 271         # issue_i starts inactive
 272         yield self.dut.issue_i.eq(0)
 273
 274         for n in range(self.MIN_BUSY_LOW):
 275             yield
 276             # busy_o must remain inactive. It cannot rise on its own.
 277             busy_o = yield self.dut.busy_o
 278             assert not busy_o
 279
 280         # activate issue_i to begin the operation cycle
 281         yield self.dut.issue_i.eq(1)
 282
 283         # at the same time, present the operation
 284         yield self.dut.oper_i.insn_type.eq(self.op)
 285         yield self.dut.oper_i.invert_a.eq(self.inv_a)
 286         yield self.dut.oper_i.imm_data.imm.eq(self.imm)
 287         yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok)
 288         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 289         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 290         yield self.dut.rdmaskn.eq(rdmaskn)
 291
 292         # give one cycle for the CompUnit to latch the data
 293         yield
 294
 295         # busy_o must keep being low in this cycle, because issue_i was
 296         # low on the previous cycle.
 297         # It cannot rise on its own.
 298         # Also, busy_o and issue_i must never be active at the same time, ever.
 299         busy_o = yield self.dut.busy_o
 300         assert not busy_o
 301
 302         # Lower issue_i
 303         yield self.dut.issue_i.eq(0)
 304
 305         # deactivate inputs along with issue_i, so we can be sure the data
 306         # was latched at the correct cycle
 307         # note: rdmaskn must be held, while busy_o is active
 308         # TODO: deactivate rdmaskn when the busy_o cycle ends
 309         yield self.dut.oper_i.insn_type.eq(0)
 310         yield self.dut.oper_i.invert_a.eq(0)
 311         yield self.dut.oper_i.imm_data.imm.eq(0)
 312         yield self.dut.oper_i.imm_data.imm_ok.eq(0)
 313         yield self.dut.oper_i.zero_a.eq(0)
 314         yield
 315
 316         # wait for busy_o to lower
 317         # timeout after self.MAX_BUSY_WAIT cycles
 318         for n in range(self.MAX_BUSY_WAIT):
 319             # sample busy_o in the current cycle
 320             busy_o = yield self.dut.busy_o
 321             if not busy_o:
 322                 # operation cycle ends when busy_o becomes inactive
 323                 break
 324             yield
 325
 326         # if busy_o is still active, a timeout has occurred
 327         # TODO: Uncomment this, once the test is complete:
 328         # assert not busy_o
 329
 330         if busy_o:
 331             print("If you are reading this, "
 332                   "it's because the above test failed, as expected,\n"
 333                   "with a timeout. It must pass, once the test is complete.")
 334             return
 335
 336         print("If you are reading this, "
 337               "it's because the above test unexpectedly passed.")
 338
 339     def rd(self, rd_idx):
 340         # wait for issue_i to rise
 341         while True:
 342             issue_i = yield self.dut.issue_i
 343             if issue_i:
 344                 break
 345             # issue_i has not risen yet, so rd must keep low
 346             rel = yield self.dut.rd.rel[rd_idx]
 347             assert not rel
 348             yield
 349
 350         # we do not want rd to rise on an immediate operand
 351         # if it is immediate, exit the process
 352         # likewise, if the read mask is active
 353         # TODO: don't exit the process, monitor rd instead to ensure it
 354         #       doesn't rise on its own
 355         if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
 356             self.rd_complete[rd_idx] = True
 357             return
 358
 359         # issue_i has risen. rel must rise on the next cycle
 360         rel = yield self.dut.rd.rel[rd_idx]
 361         assert not rel
 362
 363         # stall for additional cycles. Check that rel doesn't fall on its own
 364         for n in range(self.RD_GO_DELAY[rd_idx]):
 365             yield
 366             rel = yield self.dut.rd.rel[rd_idx]
 367             assert rel
 368
 369         # Before asserting "go", make sure "rel" has risen.
 370         # The use of Settle allows "go" to be set combinatorially,
 371         # rising on the same cycle as "rel".
 372         yield Settle()
 373         rel = yield self.dut.rd.rel[rd_idx]
 374         assert rel
 375
 376         # assert go for one cycle, passing along the operand value
 377         yield self.dut.rd.go[rd_idx].eq(1)
 378         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
 379         # check that the operand was sent to the alu
 380         # TODO: Properly check the alu protocol
 381         yield Settle()
 382         alu_input = yield self.dut.get_in(rd_idx)
 383         assert alu_input == self.operands[rd_idx]
 384         yield
 385
 386         # rel must keep high, since go was inactive in the last cycle
 387         rel = yield self.dut.rd.rel[rd_idx]
 388         assert rel
 389
 390         # finish the go one-clock pulse
 391         yield self.dut.rd.go[rd_idx].eq(0)
 392         yield self.dut.src_i[rd_idx].eq(0)
 393         yield
 394
 395         # rel must have gone low in response to go being high
 396         # on the previous cycle
 397         rel = yield self.dut.rd.rel[rd_idx]
 398         assert not rel
 399
 400         self.rd_complete[rd_idx] = True
 401
 402         # TODO: check that rel doesn't rise again until the end of the
 403         #       busy_o cycle
 404
 405     def wr(self, wr_idx):
 406         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 407         yield
 408         # TODO: also when dut.wr.go is set, check the output against the
 409         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 410
 411     def run_simulation(self, vcd_name):
 412         m = Module()
 413         m.submodules.cu = self.dut
 414         sim = Simulator(m)
 415         sim.add_clock(1e-6)
 416
 417         sim.add_sync_process(wrap(self.driver()))
 418         sim.add_sync_process(wrap(self.rd(0)))
 419         sim.add_sync_process(wrap(self.rd(1)))
 420         sim.add_sync_process(wrap(self.wr(0)))
 421         sim_writer = sim.write_vcd(vcd_name)
 422         with sim_writer:
 423             sim.run()
 424
 425
 426 def test_compunit_regspec2_fsm():
 427
 428     inspec = [('INT', 'a', '0:15'),
 429               ('INT', 'b', '0:15'),
 430             ]
 431     outspec = [('INT', 'o', '0:15'),
 432               ]
 433
 434     regspec = (inspec, outspec)
 435
 436     m = Module()
 437     alu = Shifter(8)
 438     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 439     m.submodules.cu = dut
 440
 441     sim = Simulator(m)
 442     sim.add_clock(1e-6)
 443
 444     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut)))
 445     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd')
 446     with sim_writer:
 447         sim.run()
 448
 449
 450 def test_compunit_regspec3():
 451
 452     inspec = [('INT', 'a', '0:15'),
 453               ('INT', 'b', '0:15'),
 454               ('INT', 'c', '0:15')]
 455     outspec = [('INT', 'o', '0:15'),
 456               ]
 457
 458     regspec = (inspec, outspec)
 459
 460     m = Module()
 461     alu = DummyALU(16)
 462     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 463     m.submodules.cu = dut
 464
 465     sim = Simulator(m)
 466     sim.add_clock(1e-6)
 467
 468     sim.add_sync_process(wrap(scoreboard_sim_dummy(dut)))
 469     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 470     with sim_writer:
 471         sim.run()
 472
 473
 474 def test_compunit_regspec1():
 475
 476     inspec = [('INT', 'a', '0:15'),
 477               ('INT', 'b', '0:15')]
 478     outspec = [('INT', 'o', '0:15'),
 479               ]
 480
 481     regspec = (inspec, outspec)
 482
 483     m = Module()
 484     alu = ALU(16)
 485     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 486     m.submodules.cu = dut
 487
 488     vl = rtlil.convert(dut, ports=dut.ports())
 489     with open("test_compunit_regspec1.il", "w") as f:
 490         f.write(vl)
 491
 492     sim = Simulator(m)
 493     sim.add_clock(1e-6)
 494
 495     sim.add_sync_process(wrap(scoreboard_sim(dut)))
 496     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd')
 497     with sim_writer:
 498         sim.run()
 499
 500     test = CompUnitParallelTest(dut)
 501     test.run_simulation("test_compunit_parallel.vcd")
 502
 503
 504 if __name__ == '__main__':
 505     test_compunit_fsm()
 506     test_compunit()
 507     test_compunit_regspec1()
 508     test_compunit_regspec3()