src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from soc.fu.regspec import RegSpecAPI
  12
  13 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  14 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  15 from openpower.decoder.power_decoder2 import Data
  16 from openpower.consts import MSR
  17
  18 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  19 from soc.experiment.l0_cache import PortInterface
  20 from soc.experiment.pimem import LDSTException
  21 from soc.experiment.compldst_multi import LDSTCompUnit
  22 from soc.config.test.test_loadstore import TestMemPspec
  23
  24 ########################################
  25
  26 def dcbz(dut, src1, src2, src3, imm, imm_ok=True, update=False,
  27           byterev=True):
  28     print("DCBZ", src1, src2, src3, imm, imm_ok, update)
  29     yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ)
  30     yield dut.oper_i.data_len.eq(2)  # half-word
  31     yield dut.oper_i.byte_reverse.eq(byterev)
  32     yield dut.src1_i.eq(src1)
  33     yield dut.src2_i.eq(src2)
  34     yield dut.src3_i.eq(src3)
  35     yield dut.oper_i.imm_data.data.eq(imm)
  36     yield dut.oper_i.imm_data.ok.eq(imm_ok)
  37     #FIXME: -- yield dut.oper_i.update.eq(update)
  38     yield dut.issue_i.eq(1)
  39     yield
  40     yield dut.issue_i.eq(0)
  41
  42     if imm_ok:
  43         active_rel = 0b101
  44     else:
  45         active_rel = 0b111
  46     # wait for all active rel signals to come up
  47     while True:
  48         rel = yield dut.rd.rel_o
  49         if rel == active_rel:
  50             break
  51         yield
  52     yield dut.rd.go_i.eq(active_rel)
  53     yield
  54     yield dut.rd.go_i.eq(0)
  55
  56     yield from wait_for(dut.adr_rel_o, False, test1st=True)
  57     # yield from wait_for(dut.adr_rel_o)
  58     # yield dut.ad.go.eq(1)
  59     # yield
  60     # yield dut.ad.go.eq(0)
  61
  62     if update:
  63         yield from wait_for(dut.wr.rel_o[1])
  64         yield dut.wr.go.eq(0b10)
  65         yield
  66         addr = yield dut.addr_o
  67         print("addr", addr)
  68         yield dut.wr.go.eq(0)
  69     else:
  70         addr = None
  71
  72     yield from wait_for(dut.sto_rel_o)
  73     yield dut.go_st_i.eq(1)
  74     yield
  75     yield dut.go_st_i.eq(0)
  76     yield from wait_for(dut.busy_o, False)
  77     # wait_for(dut.stwd_mem_o)
  78     yield
  79     return addr
  80
  81
  82 def ldst_sim(dut):
  83     yield from dcbz(dut, 4, 0, 3, 2) # FIXME
  84     yield
  85
  86 ########################################
  87
  88
  89 class TestLDSTCompUnitMMU(LDSTCompUnit):
  90
  91     def __init__(self, rwid, pspec):
  92         from soc.experiment.l0_cache import TstL0CacheBuffer
  93         self.l0 = l0 = TstL0CacheBuffer(pspec)
  94         pi = l0.l0.dports[0]
  95         LDSTCompUnit.__init__(self, pi, rwid, 4)
  96
  97     def elaborate(self, platform):
  98         m = LDSTCompUnit.elaborate(self, platform)
  99         m.submodules.l0 = self.l0
 100         # link addr-go direct to rel
 101         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 102         return m
 103
 104
 105 def test_scoreboard_mmu():
 106
 107     units = {}
 108     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 109                          imem_ifacetype='bare_wb',
 110                          addr_wid=48,
 111                          mask_wid=8,
 112                          reg_wid=64,
 113                          units=units)
 114
 115     dut = TestLDSTCompUnitMMU(16,pspec)
 116     vl = rtlil.convert(dut, ports=dut.ports())
 117     with open("test_ldst_comp_mmu1.il", "w") as f:
 118         f.write(vl)
 119
 120     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 121
 122 ########################################
 123 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
 124
 125     def __init__(self, pspec):
 126         from soc.experiment.l0_cache import TstL0CacheBuffer
 127         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 128         regspec = LDSTPipeSpec.regspec
 129         self.l0 = l0 = TstL0CacheBuffer(pspec)
 130         pi = l0.l0.dports[0]
 131         LDSTCompUnit.__init__(self, pi, regspec, 4)
 132
 133     def elaborate(self, platform):
 134         m = LDSTCompUnit.elaborate(self, platform)
 135         m.submodules.l0 = self.l0
 136         # link addr-go direct to rel
 137         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 138         return m
 139
 140
 141 def test_scoreboard_regspec_mmu():
 142
 143     units = {}
 144     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 145                          imem_ifacetype='bare_wb',
 146                          addr_wid=48,
 147                          mask_wid=8,
 148                          reg_wid=64,
 149                          units=units)
 150
 151     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 152     vl = rtlil.convert(dut, ports=dut.ports())
 153     with open("test_ldst_comp_mmu2.il", "w") as f:
 154         f.write(vl)
 155
 156     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 157
 158
 159 if __name__ == '__main__':
 160     test_scoreboard_regspec_mmu()
 161     #only one test for now -- test_scoreboard_mmu()