src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 #from nmigen.compat.sim import run_simulation
   4 from nmigen.sim import Simulator, Delay, Settle
   5 from nmigen.cli import verilog, rtlil
   6 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   7 from nmigen.hdl.rec import Record, Layout
   8
   9 from nmutil.latch import SRLatch, latchregister
  10 from nmutil.byterev import byte_reverse
  11 from nmutil.extend import exts
  12 from nmutil.util import wrap
  13 from soc.fu.regspec import RegSpecAPI
  14
  15 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  16 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  17 from openpower.decoder.power_decoder2 import Data
  18 from openpower.consts import MSR
  19
  20 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  21 from soc.experiment.l0_cache import PortInterface
  22 from soc.experiment.pimem import LDSTException
  23 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  24 from soc.config.test.test_loadstore import TestMemPspec
  25
  26 from soc.experiment.mmu import MMU
  27 from nmutil.util import Display
  28
  29 from soc.config.loadstore import ConfigMemoryPortInterface
  30 from soc.experiment.test import pagetables
  31 from soc.experiment.test.test_wishbone import wb_get
  32
  33 ########################################
  34
  35 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
  36 def ldst_sim(dut):
  37     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
  38     addr = 0x100e0
  39     data = 0xf553b658ba7e1f51
  40
  41     yield from store(dut, addr, 0, data, 0)
  42     yield
  43     #TODO
  44     dut.stop = True # stop simulation
  45
  46 ########################################
  47
  48
  49 class TestLDSTCompUnitMMU(LDSTCompUnit):
  50
  51     def __init__(self, rwid, pspec):
  52         from soc.experiment.l0_cache import TstL0CacheBuffer
  53         self.l0 = l0 = TstL0CacheBuffer(pspec)
  54         pi = l0.l0.dports[0]
  55         LDSTCompUnit.__init__(self, pi, rwid, 4)
  56
  57     def elaborate(self, platform):
  58         m = LDSTCompUnit.elaborate(self, platform)
  59         m.submodules.l0 = self.l0
  60         # link addr-go direct to rel
  61         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  62         return m
  63
  64
  65 def test_scoreboard_mmu():
  66
  67     units = {}
  68     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  69                          imem_ifacetype='bare_wb',
  70                          addr_wid=48,
  71                          mask_wid=8,
  72                          reg_wid=64,
  73                          units=units)
  74
  75     dut = TestLDSTCompUnitMMU(16,pspec)
  76     vl = rtlil.convert(dut, ports=dut.ports())
  77     with open("test_ldst_comp_mmu1.il", "w") as f:
  78         f.write(vl)
  79
  80     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
  81
  82 ########################################
  83 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
  84
  85     def __init__(self, pspec):
  86         from soc.experiment.l0_cache import TstL0CacheBuffer
  87         from soc.fu.ldst.pipe_data import LDSTPipeSpec
  88         regspec = LDSTPipeSpec.regspec
  89
  90         # use a LoadStore1 here
  91
  92         cmpi = ConfigMemoryPortInterface(pspec)
  93         self.cmpi = cmpi
  94         ldst = cmpi.pi
  95         self.l0 = ldst
  96
  97         self.mmu = MMU()
  98         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
  99
 100     def elaborate(self, platform):
 101         m = LDSTCompUnit.elaborate(self, platform)
 102         m.submodules.l0 = self.l0
 103         m.submodules.mmu = self.mmu
 104         # link addr-go direct to rel
 105         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 106
 107         # link mmu and dcache together
 108         dcache = self.l0.dcache
 109         mmu = self.mmu
 110         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 111         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 112
 113         return m
 114
 115
 116
 117
 118 def test_scoreboard_regspec_mmu():
 119
 120     m = Module()
 121
 122     units = {}
 123     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 124                          imem_ifacetype='bare_wb',
 125                          addr_wid=48,
 126                          mask_wid=8,
 127                          reg_wid=64,
 128                          units=units)
 129
 130     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 131
 132     m.submodules.dut = dut
 133
 134     sim = Simulator(m)
 135     sim.add_clock(1e-6)
 136
 137     dut.mem = pagetables.test1
 138     dut.stop = False
 139
 140     sim.add_sync_process(wrap(ldst_sim(dut)))
 141     sim.add_sync_process(wrap(wb_get(dut)))
 142     with sim.write_vcd('test_scoreboard_regspec_mmu'):
 143         sim.run()
 144
 145
 146 if __name__ == '__main__':
 147     test_scoreboard_regspec_mmu()
 148     #only one test for now -- test_scoreboard_mmu()