src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit.
   2
   3
   4 from nmigen.compat.sim import run_simulation
   5 from nmigen.cli import verilog, rtlil
   6 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   7 from nmigen.hdl.rec import Record, Layout
   8
   9 """
  10 from nmutil.latch import SRLatch, latchregister
  11 from nmutil.byterev import byte_reverse
  12 from nmutil.extend import exts
  13
  14 from soc.fu.regspec import RegSpecAPI
  15
  16 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  17 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  18 from openpower.decoder.power_decoder2 import Data
  19 from openpower.consts import MSR
  20 """
  21
  22 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  23 from soc.experiment.l0_cache import PortInterface
  24 from soc.experiment.pimem import LDSTException
  25 from soc.experiment.compldst_multi import LDSTCompUnit
  26 from soc.config.test.test_loadstore import TestMemPspec
  27
  28 # for debugging
  29 from nmutil.util import Display
  30
  31 ########################################
  32
  33 def ldst_sim(dut):
  34     yield Display("TODO")
  35
  36 ########################################
  37
  38
  39 class TestLDSTCompUnitMMU(LDSTCompUnit):
  40
  41     def __init__(self, rwid, pspec):
  42         from soc.experiment.l0_cache import TstL0CacheBuffer
  43         self.l0 = l0 = TstL0CacheBuffer(pspec)
  44         pi = l0.l0.dports[0]
  45         LDSTCompUnit.__init__(self, pi, rwid, 4)
  46
  47     def elaborate(self, platform):
  48         m = LDSTCompUnit.elaborate(self, platform)
  49         m.submodules.l0 = self.l0
  50         # link addr-go direct to rel
  51         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  52         return m
  53
  54
  55 def test_scoreboard_mmu():
  56
  57     units = {}
  58     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  59                          imem_ifacetype='bare_wb',
  60                          addr_wid=48,
  61                          mask_wid=8,
  62                          reg_wid=64,
  63                          units=units)
  64
  65     dut = TestLDSTCompUnitMMU(16,pspec)
  66     vl = rtlil.convert(dut, ports=dut.ports())
  67     with open("test_ldst_comp_mmu1.il", "w") as f:
  68         f.write(vl)
  69
  70     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
  71
  72 ########################################
  73 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
  74
  75     def __init__(self, pspec):
  76         from soc.experiment.l0_cache import TstL0CacheBuffer
  77         from soc.fu.ldst.pipe_data import LDSTPipeSpec
  78         regspec = LDSTPipeSpec.regspec
  79         self.l0 = l0 = TstL0CacheBuffer(pspec)
  80         pi = l0.l0.dports[0]
  81         LDSTCompUnit.__init__(self, pi, regspec, 4)
  82
  83     def elaborate(self, platform):
  84         m = LDSTCompUnit.elaborate(self, platform)
  85         m.submodules.l0 = self.l0
  86         # link addr-go direct to rel
  87         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  88         return m
  89
  90
  91 def test_scoreboard_regspec_mmu():
  92
  93     units = {}
  94     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  95                          imem_ifacetype='bare_wb',
  96                          addr_wid=48,
  97                          mask_wid=8,
  98                          reg_wid=64,
  99                          units=units)
 100
 101     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 102     vl = rtlil.convert(dut, ports=dut.ports())
 103     with open("test_ldst_comp_mmu2.il", "w") as f:
 104         f.write(vl)
 105
 106     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 107
 108
 109 if __name__ == '__main__':
 110     test_scoreboard_regspec_mmu()
 111     #only one test for now -- test_scoreboard_mmu()