src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from soc.fu.regspec import RegSpecAPI
  12
  13 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  14 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  15 from openpower.decoder.power_decoder2 import Data
  16 from openpower.consts import MSR
  17
  18 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  19 from soc.experiment.l0_cache import PortInterface
  20 from soc.experiment.pimem import LDSTException
  21 from soc.experiment.compldst_multi import LDSTCompUnit
  22 from soc.config.test.test_loadstore import TestMemPspec
  23
  24 from soc.experiment.mmu import MMU
  25 from nmutil.util import Display
  26
  27 def wait_for_debug(sig, event, wait=True, test1st=False):
  28     v = (yield sig)
  29     print("wait for", sig, v, wait, test1st)
  30     if test1st and bool(v) == wait:
  31         return
  32     while True:
  33         yield
  34         v = (yield sig)
  35         yield Display("waiting for "+event)
  36         if bool(v) == wait:
  37             break
  38
  39 # if RA = 0 then b <- 0     RA needs to be read if RA = 0
  40 # else           b <-(RA)
  41 # EA <- b + (RB)            RB needs to be read
  42 # verify that EA is correct first
  43 def dcbz(dut, ra, zero_a, rb):
  44     print("LD_part", ra, zero_a, rb)
  45     yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ)
  46     yield dut.src1_i.eq(ra)
  47     yield dut.src2_i.eq(rb)
  48     yield dut.oper_i.zero_a.eq(zero_a)
  49     yield dut.issue_i.eq(1)
  50     yield
  51     yield dut.issue_i.eq(0)
  52     yield
  53
  54     # set up operand flags
  55     rd = 0b10
  56     if not zero_a:  # no zero-a means RA needs to be read
  57         rd |= 0b01
  58
  59     # wait for the operands (RA, RB, or both)
  60     if rd:
  61         yield dut.rd.go_i.eq(rd)
  62         yield from wait_for_debug(dut.rd.rel_o,"operands (RA, RB, or both)")
  63         yield dut.rd.go_i.eq(0)
  64
  65
  66 def ldst_sim(dut):
  67     yield from dcbz(dut, 4, 0, 3) # EA=7
  68     yield
  69
  70 ########################################
  71
  72
  73 class TestLDSTCompUnitMMU(LDSTCompUnit):
  74
  75     def __init__(self, rwid, pspec):
  76         from soc.experiment.l0_cache import TstL0CacheBuffer
  77         self.l0 = l0 = TstL0CacheBuffer(pspec)
  78         pi = l0.l0.dports[0]
  79         LDSTCompUnit.__init__(self, pi, rwid, 4)
  80
  81     def elaborate(self, platform):
  82         m = LDSTCompUnit.elaborate(self, platform)
  83         m.submodules.l0 = self.l0
  84         # link addr-go direct to rel
  85         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  86         return m
  87
  88
  89 def test_scoreboard_mmu():
  90
  91     units = {}
  92     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  93                          imem_ifacetype='bare_wb',
  94                          addr_wid=48,
  95                          mask_wid=8,
  96                          reg_wid=64,
  97                          units=units)
  98
  99     dut = TestLDSTCompUnitMMU(16,pspec)
 100     vl = rtlil.convert(dut, ports=dut.ports())
 101     with open("test_ldst_comp_mmu1.il", "w") as f:
 102         f.write(vl)
 103
 104     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 105
 106 ########################################
 107 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
 108
 109     def __init__(self, pspec):
 110         from soc.experiment.l0_cache import TstL0CacheBuffer
 111         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 112         regspec = LDSTPipeSpec.regspec
 113         self.l0 = l0 = TstL0CacheBuffer(pspec) #this is wrong, see setup_mmu
 114         self.mmu = MMU()
 115         pi = l0.l0.dports[0]
 116         LDSTCompUnit.__init__(self, pi, regspec, 4)
 117
 118     def elaborate(self, platform):
 119         m = LDSTCompUnit.elaborate(self, platform)
 120         m.submodules.l0 = self.l0
 121         m.submodules.mmu = self.mmu
 122         # link addr-go direct to rel
 123         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 124
 125         # link mmu and dcache together
 126         dcache = self.l0.pimem.dcache
 127         mmu = self.mmu
 128         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 129         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 130
 131
 132         return m
 133
 134
 135 def test_scoreboard_regspec_mmu():
 136
 137     units = {}
 138     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 139                          imem_ifacetype='bare_wb',
 140                          addr_wid=48,
 141                          mask_wid=8,
 142                          reg_wid=64,
 143                          units=units)
 144
 145     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 146
 147     # TODO: setup pagetables for MMU
 148
 149     vl = rtlil.convert(dut, ports=dut.ports())
 150     with open("test_ldst_comp_mmu2.il", "w") as f:
 151         f.write(vl)
 152
 153     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 154
 155
 156 if __name__ == '__main__':
 157     test_scoreboard_regspec_mmu()
 158     #only one test for now -- test_scoreboard_mmu()