src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from soc.fu.regspec import RegSpecAPI
  12
  13 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  14 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  15 from openpower.decoder.power_decoder2 import Data
  16 from openpower.consts import MSR
  17
  18 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  19 from soc.experiment.l0_cache import PortInterface
  20 from soc.experiment.pimem import LDSTException
  21 from soc.experiment.compldst_multi import LDSTCompUnit
  22 from soc.config.test.test_loadstore import TestMemPspec
  23
  24 from soc.experiment.mmu import MMU
  25
  26 ########################################
  27 # copied from compldst_multi.py
  28 # for debugging -- remove once done
  29 def load_part(dut, src1, src2, imm, imm_ok=True, update=False, zero_a=False,
  30          byterev=True):
  31     print("LD_part", src1, src2, imm, imm_ok, update)
  32     yield dut.oper_i.insn_type.eq(MicrOp.OP_LOAD)
  33     yield dut.oper_i.data_len.eq(2)  # half-word
  34     yield dut.oper_i.byte_reverse.eq(byterev)
  35     yield dut.src1_i.eq(src1)
  36     yield dut.src2_i.eq(src2)
  37     yield dut.oper_i.zero_a.eq(zero_a)
  38     yield dut.oper_i.imm_data.imm.eq(imm)
  39     yield dut.oper_i.imm_data.ok.eq(imm_ok)
  40     yield dut.issue_i.eq(1)
  41     yield
  42     yield dut.issue_i.eq(0)
  43     yield
  44
  45     # set up read-operand flags
  46     rd = 0b00
  47     if not imm_ok:  # no immediate means RB register needs to be read
  48         rd |= 0b10
  49     if not zero_a:  # no zero-a means RA needs to be read
  50         rd |= 0b01
  51
  52     # wait for the operands (RA, RB, or both)
  53     if rd:
  54         yield dut.rd.go.eq(rd)
  55         yield from wait_for(dut.rd.rel_o)
  56         yield dut.rd.go.eq(0)
  57
  58 # if RA = 0 then b <- 0     RA needs to be read if RA = 0
  59 # else           b <-(RA)
  60 # EA <- b + (RB)            RB needs to be read
  61 # verify that EA is correct first
  62 def dcbz(dut, ra, zero_a, rb):
  63     print("LD_part", ra, zero_a, rb)
  64     yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ)
  65     yield dut.src1_i.eq(ra)
  66     yield dut.src2_i.eq(rb)
  67     yield dut.oper_i.zero_a.eq(zero_a)
  68     yield dut.issue_i.eq(1)
  69     yield
  70     yield dut.issue_i.eq(0)
  71     yield
  72
  73
  74 def ldst_sim(dut):
  75     yield from dcbz(dut, 4, 0, 3) # EA=7
  76     #yield from load_part(dut, 4, 0, 2)
  77     yield
  78
  79 ########################################
  80
  81
  82 class TestLDSTCompUnitMMU(LDSTCompUnit):
  83
  84     def __init__(self, rwid, pspec):
  85         from soc.experiment.l0_cache import TstL0CacheBuffer
  86         self.l0 = l0 = TstL0CacheBuffer(pspec)
  87         pi = l0.l0.dports[0]
  88         LDSTCompUnit.__init__(self, pi, rwid, 4)
  89
  90     def elaborate(self, platform):
  91         m = LDSTCompUnit.elaborate(self, platform)
  92         m.submodules.l0 = self.l0
  93         # link addr-go direct to rel
  94         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  95         return m
  96
  97
  98 def test_scoreboard_mmu():
  99
 100     units = {}
 101     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 102                          imem_ifacetype='bare_wb',
 103                          addr_wid=48,
 104                          mask_wid=8,
 105                          reg_wid=64,
 106                          units=units)
 107
 108     dut = TestLDSTCompUnitMMU(16,pspec)
 109     vl = rtlil.convert(dut, ports=dut.ports())
 110     with open("test_ldst_comp_mmu1.il", "w") as f:
 111         f.write(vl)
 112
 113     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 114
 115 ########################################
 116 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
 117
 118     def __init__(self, pspec):
 119         from soc.experiment.l0_cache import TstL0CacheBuffer
 120         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 121         regspec = LDSTPipeSpec.regspec
 122         self.l0 = l0 = TstL0CacheBuffer(pspec)
 123         self.mmu = MMU()
 124         pi = l0.l0.dports[0]
 125         LDSTCompUnit.__init__(self, pi, regspec, 4)
 126
 127     def elaborate(self, platform):
 128         m = LDSTCompUnit.elaborate(self, platform)
 129         m.submodules.l0 = self.l0
 130         m.submodules.mmu = self.mmu
 131         # link addr-go direct to rel
 132         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 133
 134         # link mmu and dcache together
 135         dcache = self.l0.pimem.dcache
 136         mmu = self.mmu
 137         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 138         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 139
 140
 141         return m
 142
 143
 144 def test_scoreboard_regspec_mmu():
 145
 146     units = {}
 147     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 148                          imem_ifacetype='bare_wb',
 149                          addr_wid=48,
 150                          mask_wid=8,
 151                          reg_wid=64,
 152                          units=units)
 153
 154     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 155
 156     # TODO: setup pagetables for MMU
 157
 158     vl = rtlil.convert(dut, ports=dut.ports())
 159     with open("test_ldst_comp_mmu2.il", "w") as f:
 160         f.write(vl)
 161
 162     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 163
 164
 165 if __name__ == '__main__':
 166     test_scoreboard_regspec_mmu()
 167     #only one test for now -- test_scoreboard_mmu()