src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from soc.fu.regspec import RegSpecAPI
  12
  13 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  14 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  15 from openpower.decoder.power_decoder2 import Data
  16 from openpower.consts import MSR
  17
  18 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  19 from soc.experiment.l0_cache import PortInterface
  20 from soc.experiment.pimem import LDSTException
  21 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  22 from soc.config.test.test_loadstore import TestMemPspec
  23
  24 from soc.experiment.mmu import MMU
  25 from nmutil.util import Display
  26
  27 from soc.config.loadstore import ConfigMemoryPortInterface
  28
  29 def wait_for_debug(sig, event, wait=True, test1st=False):
  30     v = (yield sig)
  31     print("wait for", sig, v, wait, test1st)
  32     if test1st and bool(v) == wait:
  33         return
  34     while True:
  35         yield
  36         v = (yield sig)
  37         yield Display("waiting for "+event)
  38         if bool(v) == wait:
  39             break
  40
  41 # if RA = 0 then b <- 0     RA needs to be read if RA = 0
  42 # else           b <-(RA)
  43 # EA <- b + (RB)            RB needs to be read
  44 # verify that EA is correct first
  45 def dcbz(dut, ra, zero_a, rb):
  46     print("LD_part", ra, zero_a, rb)
  47     yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ)
  48     yield dut.src1_i.eq(ra)
  49     yield dut.src2_i.eq(rb)
  50     yield dut.oper_i.zero_a.eq(zero_a)
  51     yield dut.issue_i.eq(1)
  52     yield
  53     yield dut.issue_i.eq(0)
  54     yield
  55
  56     # set up operand flags
  57     rd = 0b10
  58     if not zero_a:  # no zero-a means RA needs to be read
  59         rd |= 0b01
  60
  61     # wait for the operands (RA, RB, or both)
  62     if rd:
  63         yield dut.rd.go_i.eq(rd)
  64         yield from wait_for_debug(dut.rd.rel_o,"operands (RA, RB, or both)")
  65         yield dut.rd.go_i.eq(0)
  66
  67
  68
  69 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
  70 def ldst_sim(dut):
  71     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
  72     ###yield from dcbz(dut, 4, 0, 3) # EA=7
  73     addr = 0x100e0
  74     data = 0xf553b658ba7e1f51
  75
  76     yield from store(dut, addr, 0, data, 0)
  77     yield
  78     yield from load(dut, 4, 0, 2) #FIXME
  79     """
  80     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
  81     assert ld_data == 0xf553b658ba7e1f51
  82     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
  83     assert ld_data == 0xf553b658ba7e1f51
  84     """
  85     yield
  86
  87 ########################################
  88
  89
  90 class TestLDSTCompUnitMMU(LDSTCompUnit):
  91
  92     def __init__(self, rwid, pspec):
  93         from soc.experiment.l0_cache import TstL0CacheBuffer
  94         self.l0 = l0 = TstL0CacheBuffer(pspec)
  95         pi = l0.l0.dports[0]
  96         LDSTCompUnit.__init__(self, pi, rwid, 4)
  97
  98     def elaborate(self, platform):
  99         m = LDSTCompUnit.elaborate(self, platform)
 100         m.submodules.l0 = self.l0
 101         # link addr-go direct to rel
 102         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 103         return m
 104
 105
 106 def test_scoreboard_mmu():
 107
 108     units = {}
 109     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 110                          imem_ifacetype='bare_wb',
 111                          addr_wid=48,
 112                          mask_wid=8,
 113                          reg_wid=64,
 114                          units=units)
 115
 116     dut = TestLDSTCompUnitMMU(16,pspec)
 117     vl = rtlil.convert(dut, ports=dut.ports())
 118     with open("test_ldst_comp_mmu1.il", "w") as f:
 119         f.write(vl)
 120
 121     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 122     #TODO add wb runner here
 123
 124
 125 ########################################
 126 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
 127
 128     def __init__(self, pspec):
 129         from soc.experiment.l0_cache import TstL0CacheBuffer
 130         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 131         regspec = LDSTPipeSpec.regspec
 132
 133         # use a LoadStore1 here
 134
 135         cmpi = ConfigMemoryPortInterface(pspec)
 136         self.cmpi = cmpi
 137         ldst = cmpi.pi
 138         self.l0 = ldst
 139
 140         self.mmu = MMU()
 141         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
 142
 143     def elaborate(self, platform):
 144         m = LDSTCompUnit.elaborate(self, platform)
 145         m.submodules.l0 = self.l0
 146         m.submodules.mmu = self.mmu
 147         # link addr-go direct to rel
 148         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 149
 150         # link mmu and dcache together
 151         dcache = self.l0.dcache
 152         mmu = self.mmu
 153         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 154         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 155
 156         # TODO: link wishbone bus
 157
 158         return m
 159
 160
 161 def test_scoreboard_regspec_mmu():
 162
 163     units = {}
 164     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 165                          imem_ifacetype='bare_wb',
 166                          addr_wid=48,
 167                          mask_wid=8,
 168                          reg_wid=64,
 169                          units=units)
 170
 171     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 172
 173     # TODO: setup pagetables for MMU
 174
 175     vl = rtlil.convert(dut, ports=dut.ports())
 176     with open("test_ldst_comp_mmu2.il", "w") as f:
 177         f.write(vl)
 178
 179     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 180
 181
 182 if __name__ == '__main__':
 183     test_scoreboard_regspec_mmu()
 184     #only one test for now -- test_scoreboard_mmu()