src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit.
   2
   3
   4 from nmigen.compat.sim import run_simulation
   5 from nmigen.cli import verilog, rtlil
   6 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   7 from nmigen.hdl.rec import Record, Layout
   8
   9 """
  10 from nmutil.latch import SRLatch, latchregister
  11 from nmutil.byterev import byte_reverse
  12 from nmutil.extend import exts
  13
  14 from soc.fu.regspec import RegSpecAPI
  15
  16 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  17 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  18 from openpower.decoder.power_decoder2 import Data
  19 from openpower.consts import MSR
  20 """
  21
  22 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  23 from soc.experiment.l0_cache import PortInterface
  24 from soc.experiment.pimem import LDSTException
  25 from soc.experiment.compldst_multi import LDSTCompUnit
  26 from soc.config.test.test_loadstore import TestMemPspec
  27
  28 ########################################
  29
  30 def ldst_sim(dut):
  31     print("TODO")
  32     yield
  33
  34 ########################################
  35
  36
  37 class TestLDSTCompUnitMMU(LDSTCompUnit):
  38
  39     def __init__(self, rwid, pspec):
  40         from soc.experiment.l0_cache import TstL0CacheBuffer
  41         self.l0 = l0 = TstL0CacheBuffer(pspec)
  42         pi = l0.l0.dports[0]
  43         LDSTCompUnit.__init__(self, pi, rwid, 4)
  44
  45     def elaborate(self, platform):
  46         m = LDSTCompUnit.elaborate(self, platform)
  47         m.submodules.l0 = self.l0
  48         # link addr-go direct to rel
  49         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  50         return m
  51
  52
  53 def test_scoreboard_mmu():
  54
  55     units = {}
  56     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  57                          imem_ifacetype='bare_wb',
  58                          addr_wid=48,
  59                          mask_wid=8,
  60                          reg_wid=64,
  61                          units=units)
  62
  63     dut = TestLDSTCompUnitMMU(16,pspec)
  64     vl = rtlil.convert(dut, ports=dut.ports())
  65     with open("test_ldst_comp_mmu1.il", "w") as f:
  66         f.write(vl)
  67
  68     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
  69
  70 ########################################
  71 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
  72
  73     def __init__(self, pspec):
  74         from soc.experiment.l0_cache import TstL0CacheBuffer
  75         from soc.fu.ldst.pipe_data import LDSTPipeSpec
  76         regspec = LDSTPipeSpec.regspec
  77         self.l0 = l0 = TstL0CacheBuffer(pspec)
  78         pi = l0.l0.dports[0]
  79         LDSTCompUnit.__init__(self, pi, regspec, 4)
  80
  81     def elaborate(self, platform):
  82         m = LDSTCompUnit.elaborate(self, platform)
  83         m.submodules.l0 = self.l0
  84         # link addr-go direct to rel
  85         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  86         return m
  87
  88
  89 def test_scoreboard_regspec_mmu():
  90
  91     units = {}
  92     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  93                          imem_ifacetype='bare_wb',
  94                          addr_wid=48,
  95                          mask_wid=8,
  96                          reg_wid=64,
  97                          units=units)
  98
  99     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 100     vl = rtlil.convert(dut, ports=dut.ports())
 101     with open("test_ldst_comp_mmu2.il", "w") as f:
 102         f.write(vl)
 103
 104     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 105
 106
 107 if __name__ == '__main__':
 108     test_scoreboard_regspec_mmu()
 109     #only one test for now -- test_scoreboard_mmu()