src/soc/experiment/test/test_compldst_multi_mmu_fsm.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from nmutil.util import wrap
  12 from soc.fu.regspec import RegSpecAPI
  13
  14 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  15 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  16 from openpower.decoder.power_decoder2 import Data
  17 from openpower.consts import MSR
  18
  19 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  20 from soc.experiment.l0_cache import PortInterface
  21 from soc.experiment.pimem import LDSTException
  22 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  23 from soc.config.test.test_loadstore import TestMemPspec
  24
  25 from soc.experiment.mmu import MMU
  26 from nmutil.util import Display
  27
  28 from soc.config.loadstore import ConfigMemoryPortInterface
  29 from soc.experiment.test import pagetables
  30 from soc.experiment.test.test_wishbone import wb_get
  31
  32 # new unit added to this test case
  33 from soc.fu.mmu.pipe_data import MMUPipeSpec
  34 from soc.fu.mmu.fsm import FSMMMUStage
  35
  36 # for sending instructions to the FSM
  37 from openpower.consts import MSR
  38 from openpower.decoder.power_fields import DecodeFields
  39 from openpower.decoder.power_fieldsn import SignalBitRange
  40 from openpower.decoder.power_decoder2 import decode_spr_num
  41 from openpower.decoder.power_enums import MicrOp
  42
  43
  44 def test_TLBIE(dut):
  45     yield dut.fsm.p.i_data.ctx.op.eq(MicrOp.OP_TLBIE)
  46     yield dut.fsm.p.valid_i.eq(1)
  47     yield
  48     yield dut.fsm.p.valid_i.eq(0)
  49     yield
  50     yield
  51     yield
  52     yield
  53     yield Display("OP_TLBIE test done")
  54
  55
  56 def ldst_sim(dut):
  57     yield dut.mmu.rin.prtbl.eq(0x1000000)  # set process table
  58     addr = 0x100e0
  59     data = 0xFF  # just a single byte for this test
  60     #data = 0xf553b658ba7e1f51
  61
  62     yield from store(dut, addr, 0, data, 0)
  63     yield
  64     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  65     print(data, data_ok, ld_addr)
  66     assert(ld_data == data)
  67     yield
  68     yield from test_TLBIE(dut)
  69
  70     """
  71     -- not testing dzbz here --
  72     data = 0
  73
  74     print("doing dcbz/store with data 0 .....")
  75     yield from store_debug(dut, addr, 0, data, 0, dcbz=True) #hangs
  76
  77     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  78     print(data,data_ok,ld_addr)
  79     print("ld_data is")
  80     print(ld_data)
  81     assert(ld_data==data)
  82     print("dzbz test passed")
  83     """
  84
  85     dut.stop = True  # stop simulation
  86
  87 ########################################
  88
  89
  90 class TestLDSTCompUnitMMUFSM(LDSTCompUnit):
  91
  92     def __init__(self, rwid, pspec):
  93         from soc.experiment.l0_cache import TstL0CacheBuffer
  94         self.l0 = l0 = TstL0CacheBuffer(pspec)
  95         pi = l0.l0.dports[0]
  96         LDSTCompUnit.__init__(self, pi, rwid, 4)
  97
  98     def elaborate(self, platform):
  99         m = LDSTCompUnit.elaborate(self, platform)
 100         m.submodules.l0 = self.l0
 101         # link addr-go direct to rel
 102         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 103         return m
 104
 105
 106 def test_scoreboard_mmu():
 107
 108     units = {}
 109     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 110                          imem_ifacetype='bare_wb',
 111                          addr_wid=48,
 112                          mask_wid=8,
 113                          reg_wid=64,
 114                          units=units)
 115
 116     dut = TestLDSTCompUnit(16, pspec)
 117     vl = rtlil.convertMMUFSM(dut, ports=dut.ports())
 118     with open("test_ldst_comp_mmu1.il", "w") as f:
 119         f.write(vl)
 120
 121     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 122
 123 ########################################
 124
 125
 126 class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
 127
 128     def __init__(self, pspec):
 129         from soc.experiment.l0_cache import TstL0CacheBuffer
 130         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 131         regspec = LDSTPipeSpec.regspec
 132
 133         # use a LoadStore1 here
 134
 135         cmpi = ConfigMemoryPortInterface(pspec)
 136         self.cmpi = cmpi
 137         ldst = cmpi.pi
 138         self.l0 = ldst
 139
 140         self.mmu = MMU()
 141
 142         pipe_spec = MMUPipeSpec(id_wid=2, parent_pspec=None)
 143         self.fsm = FSMMMUStage(pipe_spec)
 144
 145         self.fsm.set_ldst_interface(ldst)
 146
 147         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
 148
 149     def elaborate(self, platform):
 150         m = LDSTCompUnit.elaborate(self, platform)
 151         m.submodules.l0 = self.l0
 152         m.submodules.mmu = self.mmu
 153         m.submodules.fsm = self.fsm
 154         # link addr-go direct to rel
 155         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 156
 157         # link mmu and dcache together
 158         dcache = self.l0.dcache
 159         mmu = self.mmu
 160         m.d.comb += dcache.m_in.eq(mmu.d_out)  # MMUToDCacheType
 161         m.d.comb += mmu.d_in.eq(dcache.m_out)  # DCacheToMMUType
 162
 163         return m
 164
 165
 166 def test_scoreboard_regspec_mmufsm():
 167
 168     m = Module()
 169
 170     units = {}
 171     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 172                          imem_ifacetype='bare_wb',
 173                          addr_wid=48,
 174                          mask_wid=8,
 175                          reg_wid=64,
 176                          units=units)
 177
 178     dut = TestLDSTCompUnitRegSpecMMUFSM(pspec)
 179
 180     m.submodules.dut = dut
 181
 182     sim = Simulator(m)
 183     sim.add_clock(1e-6)
 184
 185     dut.mem = pagetables.test1
 186     dut.stop = False
 187
 188     sim.add_sync_process(wrap(ldst_sim(dut)))  # rename ?
 189     sim.add_sync_process(wrap(wb_get(dut)))
 190     with sim.write_vcd('test_scoreboard_regspec_mmufsm.vcd'):
 191         sim.run()
 192
 193
 194 if __name__ == '__main__':
 195     test_scoreboard_regspec_mmufsm()
 196     # only one test for now -- test_scoreboard_mmu()