src/soc/experiment/test/test_l0_cache_buffer2.py

   1 """
   2 test cases for LDSTSplitter and L0CacheBuffer2
   3 """
   4
   5 from soc.experiment.l0_cache import L0CacheBuffer2
   6 from nmigen import Module, Signal, Mux, Elaboratable, Cat, Const
   7 from nmigen.cli import rtlil
   8 from soc.scoreboard.addr_split import LDSTSplitter
   9 from soc.scoreboard.addr_match import LenExpand
  10
  11 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  12
  13 from soc.experiment.pimem import PortInterfaceBase
  14
  15 from nmigen.compat.sim import run_simulation, Settle
  16
  17 class TestCachedMemoryPortInterface(PortInterfaceBase):
  18     """TestCacheMemoryPortInterface
  19
  20     This is a test class for simple verification of LDSTSplitter
  21     conforming to PortInterface
  22     """
  23
  24     def __init__(self, regwid=64, addrwid=4):
  25         super().__init__(regwid, addrwid)
  26         self.ldst = LDSTSplitter(32, 48, 4)
  27
  28     def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
  29         m.d.comb += self.ldst.addr_i.eq(addr)
  30
  31     def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
  32         m.d.comb += self.ldst.addr_i.eq(addr)
  33
  34     def set_wr_data(self, m, data, wen):
  35         m.d.comb += self.ldst.st_data_i.data.eq(data)  # write st to mem
  36         m.d.comb += self.ldst.is_st_i.eq(wen)  # enable writes
  37         st_ok = Const(1, 1)
  38         return st_ok
  39
  40     def get_rd_data(self, m):
  41         # this path is still untested
  42         ld_ok = Const(1, 1)
  43         return self.ldst.ld_data_o.data, ld_ok
  44
  45     def elaborate(self, platform):
  46         m = super().elaborate(platform)
  47
  48         # add TestMemory as submodule
  49         m.submodules.ldst = self.ldst
  50
  51         return m
  52
  53     def ports(self):
  54         yield from super().ports()
  55         # TODO: memory ports
  56
  57
  58 def test_cache_single_run(dut):
  59     #test single byte
  60     addr = 0
  61     data = 0xfeedface
  62     yield from pi_st(dut.pi, addr, data, 1)
  63
  64 def test_cache_single():
  65     dut = TestCachedMemoryPortInterface()
  66     #LDSTSplitter(8, 48, 4) #data leng in bytes, address bits, select bits
  67
  68     run_simulation(dut, test_cache_single_run(dut),
  69                    vcd_name='test_cache_single.vcd')
  70
  71
  72 if __name__ == '__main__':
  73     test_cache_single()