src/soc/experiment/test/test_ldst_pi.py

   1 """MMU PortInterface Test
   2
   3 quite basic, goes directly to the MMU to assert signals (does not
   4 yet use PortInterface)
   5 """
   6
   7 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   8 from nmigen.cli import main
   9 from nmigen.cli import rtlil
  10 from nmutil.mask import Mask, masked
  11 from nmutil.util import Display
  12
  13 if True:
  14     from nmigen.back.pysim import Simulator, Delay, Settle
  15 else:
  16     from nmigen.sim.cxxsim import Simulator, Delay, Settle
  17 from nmutil.util import wrap
  18
  19 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.config.loadstore import ConfigMemoryPortInterface
  22
  23 from soc.fu.ldst.loadstore import LoadStore1
  24 from soc.experiment.mmu import MMU
  25
  26 from nmigen.compat.sim import run_simulation
  27
  28
  29 stop = False
  30
  31 def wb_get(wb):
  32     """simulator process for getting memory load requests
  33     """
  34
  35     global stop
  36
  37     def b(x):
  38         return int.from_bytes(x.to_bytes(8, byteorder='little'),
  39                               byteorder='big', signed=False)
  40
  41     mem = {0x10000:    # PARTITION_TABLE_2
  42                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  43            b(0x800000000100000b),
  44
  45            0x30000:     # RADIX_ROOT_PTE
  46                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  47            b(0x8000000000040009),
  48
  49            0x40000:     # RADIX_SECOND_LEVEL
  50                         #          V = 1 L = 1 SW = 0 RPN = 0
  51                            # R = 1 C = 1 ATT = 0 EAA 0x7
  52            b(0xc000000000000187),
  53
  54           0x1000000:   # PROCESS_TABLE_3
  55                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  56            b(0x40000000000300ad),
  57
  58          # data to return
  59           0x1000: 0xdeadbeef01234567
  60           }
  61
  62     while not stop:
  63         while True: # wait for dc_valid
  64             if stop:
  65                 return
  66             cyc = yield (wb.cyc)
  67             stb = yield (wb.stb)
  68             if cyc and stb:
  69                 break
  70             yield
  71         addr = (yield wb.adr) << 3
  72         if addr not in mem:
  73             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  74
  75         data = mem.get(addr, 0)
  76         yield wb.dat_r.eq(data)
  77         print ("    DCACHE get %x data %x" % (addr, data))
  78         yield wb.ack.eq(1)
  79         yield
  80         yield wb.ack.eq(0)
  81
  82
  83 def mmu_lookup(dut, addr):
  84     mmu = dut.submodules.mmu
  85     global stop
  86
  87     print("pi_ld")
  88     data = yield from pi_ld(dut.submodules.ldst.pi, addr, 4, msr_pr=1)
  89     print("pi_ld done, data", hex(data))
  90     """
  91     # original test code kept for reference
  92     while not stop: # wait for dc_valid / err
  93         print("waiting for mmu")
  94         l_done = yield (mmu.l_out.done)
  95         l_err = yield (mmu.l_out.err)
  96         l_badtree = yield (mmu.l_out.badtree)
  97         l_permerr = yield (mmu.l_out.perm_error)
  98         l_rc_err = yield (mmu.l_out.rc_error)
  99         l_segerr = yield (mmu.l_out.segerr)
 100         l_invalid = yield (mmu.l_out.invalid)
 101         if (l_done or l_err or l_badtree or
 102             l_permerr or l_rc_err or l_segerr or l_invalid):
 103             break
 104         yield
 105     """
 106     phys_addr = yield mmu.d_out.addr
 107     pte = yield mmu.d_out.pte
 108     l_done = yield (mmu.l_out.done)
 109     l_err = yield (mmu.l_out.err)
 110     l_badtree = yield (mmu.l_out.badtree)
 111     print ("translated done %d err %d badtree %d addr %x pte %x" % \
 112                (l_done, l_err, l_badtree, phys_addr, pte))
 113     yield
 114     yield mmu.l_in.valid.eq(0)
 115
 116     return phys_addr
 117
 118
 119 def ldst_sim(dut):
 120     mmu = dut.submodules.mmu
 121     global stop
 122     yield mmu.rin.prtbl.eq(0x1000000) # set process table
 123     yield
 124
 125     addr = 0x1000
 126     print("pi_ld")
 127
 128     # TODO mmu_lookup using port interface
 129     # set inputs
 130     phys_addr = yield from mmu_lookup(dut, addr)
 131     #assert phys_addr == addr # happens to be the same (for this example)
 132
 133     phys_addr = yield from mmu_lookup(dut, addr)
 134     #assert phys_addr == addr # happens to be the same (for this example)
 135
 136     stop = True
 137
 138
 139 def test_mmu():
 140
 141     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 142                          imem_ifacetype='',
 143                          addr_wid=48,
 144                          #disable_cache=True, # hmmm...
 145                          mask_wid=8,
 146                          reg_wid=64)
 147
 148     m = Module()
 149     comb = m.d.comb
 150     cmpi = ConfigMemoryPortInterface(pspec)
 151     m.submodules.ldst = ldst = cmpi.pi
 152     m.submodules.mmu = mmu = MMU()
 153     dcache = ldst.dcache
 154
 155     l_in, l_out = mmu.l_in, mmu.l_out
 156     d_in, d_out = dcache.d_in, dcache.d_out
 157     wb_out, wb_in = dcache.wb_out, dcache.wb_in
 158
 159     # link mmu and dcache together
 160     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 161     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 162
 163     # link ldst and MMU together
 164     comb += l_in.eq(ldst.m_out)
 165     comb += ldst.m_in.eq(l_out)
 166
 167
 168     # nmigen Simulation
 169     sim = Simulator(m)
 170     sim.add_clock(1e-6)
 171
 172     sim.add_sync_process(wrap(ldst_sim(m)))
 173     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus())))
 174     with sim.write_vcd('test_ldst_pi.vcd'):
 175         sim.run()
 176
 177
 178 if __name__ == '__main__':
 179     test_mmu()