1 """MMU PortInterface Test
3 quite basic, goes directly to the MMU to assert signals (does not
7 from nmigen
import (C
, Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
, Signal
)
8 from nmigen
.cli
import main
9 from nmigen
.cli
import rtlil
10 from nmutil
.mask
import Mask
, masked
11 from nmutil
.util
import Display
14 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
16 from nmigen
.sim
.cxxsim
import Simulator
, Delay
, Settle
17 from nmutil
.util
import wrap
19 from soc
.config
.test
.test_pi2ls
import pi_ld
, pi_st
, pi_ldst
20 from soc
.config
.test
.test_loadstore
import TestMemPspec
21 from soc
.config
.loadstore
import ConfigMemoryPortInterface
23 from soc
.fu
.ldst
.loadstore
import LoadStore1
24 from soc
.experiment
.mmu
import MMU
26 from nmigen
.compat
.sim
import run_simulation
32 """simulator process for getting memory load requests
38 return int.from_bytes(x
.to_bytes(8, byteorder
='little'),
39 byteorder
='big', signed
=False)
41 mem
= {0x10000: # PARTITION_TABLE_2
42 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
43 b(0x800000000100000b),
45 0x30000: # RADIX_ROOT_PTE
46 # V = 1 L = 0 NLB = 0x400 NLS = 9
47 b(0x8000000000040009),
49 0x40000: # RADIX_SECOND_LEVEL
50 # V = 1 L = 1 SW = 0 RPN = 0
51 # R = 1 C = 1 ATT = 0 EAA 0x7
52 b(0xc000000000000187),
54 0x1000000: # PROCESS_TABLE_3
55 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
56 b(0x40000000000300ad),
59 0x1000: 0xdeadbeef01234567,
60 0x1008: 0xfeedf00ff001a5a5
64 while True: # wait for dc_valid
72 addr
= (yield wb
.adr
) << 3
74 print (" WB LOOKUP NO entry @ %x, returning zero" % (addr
))
76 data
= mem
.get(addr
, 0)
77 yield wb
.dat_r
.eq(data
)
78 print (" DCACHE get %x data %x" % (addr
, data
))
85 def mmu_lookup(dut
, addr
):
86 mmu
= dut
.submodules
.mmu
89 print("pi_ld", hex(addr
))
90 data
= yield from pi_ld(dut
.submodules
.ldst
.pi
, addr
, 4, msr_pr
=1)
91 print("pi_ld done, data", hex(data
))
93 # original test code kept for reference
94 while not stop: # wait for dc_valid / err
95 print("waiting for mmu")
96 l_done = yield (mmu.l_out.done)
97 l_err = yield (mmu.l_out.err)
98 l_badtree = yield (mmu.l_out.badtree)
99 l_permerr = yield (mmu.l_out.perm_error)
100 l_rc_err = yield (mmu.l_out.rc_error)
101 l_segerr = yield (mmu.l_out.segerr)
102 l_invalid = yield (mmu.l_out.invalid)
103 if (l_done or l_err or l_badtree or
104 l_permerr or l_rc_err or l_segerr or l_invalid):
108 phys_addr
= yield mmu
.d_out
.addr
109 pte
= yield mmu
.d_out
.pte
110 l_done
= yield (mmu
.l_out
.done
)
111 l_err
= yield (mmu
.l_out
.err
)
112 l_badtree
= yield (mmu
.l_out
.badtree
)
113 print ("translated done %d err %d badtree %d addr %x pte %x" % \
114 (l_done
, l_err
, l_badtree
, phys_addr
, pte
))
116 yield mmu
.l_in
.valid
.eq(0)
122 mmu
= dut
.submodules
.mmu
124 yield mmu
.rin
.prtbl
.eq(0x1000000) # set process table
127 # expecting this data to return
128 # 0x1000: 0xdeadbeef01234567,
129 # 0x1008: 0xfeedf00ff001a5a5
134 # TODO mmu_lookup using port interface
136 data
= yield from mmu_lookup(dut
, addr
)
137 assert data
== 0x1234567
139 data
= yield from mmu_lookup(dut
, addr
+8)
140 assert data
== 0xf001a5a5
141 #assert phys_addr == addr # happens to be the same (for this example)
143 data
= yield from mmu_lookup(dut
, addr
+4)
144 assert data
== 0xdeadbeef
146 data
= yield from mmu_lookup(dut
, addr
+8)
147 assert data
== 0xf001a5a5
157 pspec
= TestMemPspec(ldst_ifacetype
='mmu_cache_wb',
160 #disable_cache=True, # hmmm...
166 cmpi
= ConfigMemoryPortInterface(pspec
)
167 m
.submodules
.ldst
= ldst
= cmpi
.pi
168 m
.submodules
.mmu
= mmu
= MMU()
171 l_in
, l_out
= mmu
.l_in
, mmu
.l_out
172 d_in
, d_out
= dcache
.d_in
, dcache
.d_out
173 wb_out
, wb_in
= dcache
.wb_out
, dcache
.wb_in
175 # link mmu and dcache together
176 m
.d
.comb
+= dcache
.m_in
.eq(mmu
.d_out
) # MMUToDCacheType
177 m
.d
.comb
+= mmu
.d_in
.eq(dcache
.m_out
) # DCacheToMMUType
179 # link ldst and MMU together
180 comb
+= l_in
.eq(ldst
.m_out
)
181 comb
+= ldst
.m_in
.eq(l_out
)
188 sim
.add_sync_process(wrap(ldst_sim(m
)))
189 sim
.add_sync_process(wrap(wb_get(cmpi
.wb_bus())))
190 with sim
.write_vcd('test_ldst_pi.vcd'):
194 if __name__
== '__main__':