src/soc/experiment/test/test_wishbone.py

   1 def wb_get(dut):
   2     """simulator process for getting memory load requests
   3     """
   4     mem = dut.mem
   5     wb = dut.cmpi.wb_bus()
   6
   7     while not dut.stop:
   8         while True: # wait for dc_valid
   9             if dut.stop:
  10                 return
  11             cyc = yield (wb.cyc)
  12             stb = yield (wb.stb)
  13             if cyc and stb:
  14                 break
  15             yield
  16         addr = (yield wb.adr) << 3
  17         if addr not in mem:
  18             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  19
  20         # read or write?
  21         we = (yield wb.we)
  22         if we:
  23             store = (yield wb.dat_w)
  24             sel = (yield wb.sel)
  25             data = mem.get(addr, 0)
  26             # note we assume 8-bit sel, here
  27             res = 0
  28             for i in range(8):
  29                 mask = 0xff << (i*8)
  30                 if sel & (1<<i):
  31                     res |= store & mask
  32                 else:
  33                     res |= data & mask
  34             mem[addr] = res
  35             print ("    DCACHE set %x mask %x data %x" % (addr, sel, res))
  36         else:
  37             data = mem.get(addr, 0)
  38             yield wb.dat_r.eq(data)
  39             print ("    DCACHE get %x data %x" % (addr, data))
  40
  41         yield wb.ack.eq(1)
  42         yield
  43         yield wb.ack.eq(0)
  44         yield