src/soc/experiment/testmem.py

   1 from nmigen import Module, Elaboratable, Memory
   2
   3
   4 class TestMemory(Elaboratable):
   5     def __init__(self, regwid, addrw, granularity=None, init=True):
   6         self.ddepth = 1 # regwid //8
   7         depth = (1<<addrw) // self.ddepth
   8         self.depth = depth
   9         self.regwid = regwid
  10         print ("test memory", regwid, depth)
  11         if init is True:
  12             init = range(0, depth*2, 2)
  13         else:
  14             init = None
  15         self.mem = Memory(width=regwid, depth=depth, init=init)
  16         self.rdport = self.mem.read_port() # not now transparent=False)
  17         self.wrport = self.mem.write_port(granularity=granularity)
  18
  19     def elaborate(self, platform):
  20         m = Module()
  21         m.submodules.rdport = self.rdport
  22         m.submodules.wrport = self.wrport
  23         return m
  24
  25     def __iter__(self):
  26         yield self.rdport.addr
  27         yield self.rdport.data
  28         #yield self.rdport.en
  29         yield self.wrport.addr
  30         yield self.wrport.data
  31         yield self.wrport.en
  32
  33     def ports(self):
  34         return list(self)