src/soc/experiment/testmem.py

   1 from nmigen import Module, Elaboratable, Memory
   2
   3
   4 class TestMemory(Elaboratable):
   5     def __init__(self, regwid, addrw, granularity=None, init=True,
   6                  readonly=False):
   7         self.readonly = readonly
   8         self.ddepth = 1  # regwid //8
   9         depth = (1 << addrw) // self.ddepth
  10         self.depth = depth
  11         self.regwid = regwid
  12         print("test memory width depth", regwid, depth)
  13         if init is True:
  14             init = range(0, depth*2, 2)
  15         else:
  16             init = None
  17         self.mem = Memory(width=regwid, depth=depth, init=init)
  18         self.rdport = self.mem.read_port()  # not now transparent=False)
  19         if self.readonly:
  20             return
  21         self.wrport = self.mem.write_port(granularity=granularity)
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         m.submodules.rdport = self.rdport
  26         if self.readonly:
  27             return m
  28         m.submodules.wrport = self.wrport
  29         return m
  30
  31     def __iter__(self):
  32         yield self.rdport.addr
  33         yield self.rdport.data
  34         # yield self.rdport.en
  35         if self.readonly:
  36             return
  37         yield self.wrport.addr
  38         yield self.wrport.data
  39         yield self.wrport.en
  40
  41     def ports(self):
  42         return list(self)